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Contents

README

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π142M30

2Pai Semi · Digital Isolators · SOIC-16

π142M30 from 2Pai Semi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, operating range 3 V to 5.5 V with a 0.1 µF to 10 µF bypass capacitor to GND1.
2 GND1 power_in Ground 1, the ground reference for isolator side 1.
3 VIA input Logic input A.
4 VIB input Logic input B.
5 VOC output Logic output C.
6 VOD output Logic output D.
7 NC unconnected No connect for π142M3X (this pin is EN1 output enable only on π142M6X).
8 GND1 power_in Ground 1, the ground reference for isolator side 1.
9 GND2 power_in Ground 2, the ground reference for isolator side 2.
10 NC unconnected No connect for π142M3X (this pin is EN2 output enable only on π142M6X).
11 VID input Logic input D.
12 VIC input Logic input C.
13 VOB output Logic output B.
14 VOA output Logic output A.
15 GND2 power_in Ground 2, the ground reference for isolator side 2.
16 VDD2 power_in Supply voltage for isolator side 2, operating range 3 V to 5.5 V with a 0.1 µF to 10 µF bypass capacitor to GND2.

Key specifications

Parameter Value
Manufacturer 2Pai Semi
Package SOIC-16
Category Communication Interface Chip/UART/485/232
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDDx 3 5.5 V 3
High Level Output Current IOH -6 mA 4
Low Level Output Current IOL 6 mA 4
Data Rate 0 10 Mbps 4
Junction Temperature TJ -40 150 °C 4
Ambient Operating Temperature TA -40 125 °C 4
Supply Voltages VDD1-GND1, VDD2-GND2 -0.5 7 V TA = 25°C 3
Average Output Current per Pin, Side 1 IO1 -10 10 mA TA = 25°C 3
Average Output Current per Pin, Side 2 IO2 -10 10 mA TA = 25°C 3
Common-Mode Transients Immunity -200 200 kV/µs TA = 25°C 3
Storage Temperature Range TST -65 150 °C TA = 25°C 3
Ambient Operating Temperature Range TA -40 125 °C TA = 25°C 3
Minimum Pulse Width PW 100 ns Within pulse width distortion (PWD) limit 4
Maximum Data Rate 10 Mbps Within PWD limit 5
Propagation Delay Time tpHL, tpLH 5.5 8 12.5 ns 5VDC supply 5
Propagation Delay Time tpHL, tpLH 6.5 9 13.5 ns 3.3VDC supply 5
Pulse Width Distortion PWD 0.3 3 ns 5VDC supply, /tpHL - tpLH/ 5
Pulse Width Distortion PWD 0.4 3 ns 3.3VDC supply, /tpHL - tpLH/ 5
Part to Part Propagation Delay Skew tPSK 2 ns 5VDC supply 5
Channel to Channel Propagation Delay Skew tCSK 1.8 ns 5VDC supply 5
Channel to Channel Propagation Delay Skew tCSK 2 ns 3.3VDC supply 5
ESD (HBM) ESD -8 8 kV 5
Total Supply Current Side 1, 10 Mbps IDD1 1.94 2.91 mA 5VDC, CL = 0 pF, 10 Mbps 8
Total Supply Current Side 2, 10 Mbps IDD2 1.94 2.91 mA 5VDC, CL = 0 pF, 10 Mbps 8
Total Supply Current Side 1, 10 Mbps IDD1 1.54 2.31 mA 3.3VDC, CL = 0 pF, 10 Mbps 8
Total Supply Current Side 2, 10 Mbps IDD2 1.54 2.31 mA 3.3VDC, CL = 0 pF, 10 Mbps 8
Total Supply Current Side 1, 1 Mbps IDD1 1.16 1.74 mA 5VDC, CL = 0 pF, 1 Mbps 8
Total Supply Current Side 1, 150 Kbps IDD1 1.08 1.62 mA 5VDC, CL = 0 pF, 150 Kbps 8
Common-Mode Transient Immunity CMTI 75 kV/µs VIN = VDDx or 0V, VCM = 1000 V 5
Rated Dielectric Insulation Voltage 3000 V rms 1-minute duration 9
IC Junction to Ambient Thermal Resistance θJA 100 °C/W Thermocouple located at center of package underside 9

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN V VDE V 0884-11, each π140M3x/π141M3x/π142M3x is proof tested by applying an insulation test voltage ≥ 848 V peak for 1 sec (partial discharge detection limit = 5 pC); each π140 10

CAD (KiCad official)

  • Symbol: π142M30
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 142m30-etched.step / 142m30-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 142m30.step / 142m30.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 2Pai Semi datasheet (20 pp, sha256 85b22c927af6ccc5, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF