component
π142E60
Public Made by Adomby adom
2Pai Semi Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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π142E60
2Pai Semi · Digital Isolators · SOIC-16-300mil
π142E60 from 2Pai Semi, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Primary-side isolator supply; the datasheet gives a 3.0 V to 5.5 V supply range and a VDDx undervoltage threshold of 2.30 V to 2.95 V. |
| 2 | GND1 | power_in | Primary-side supply reference ground for VDD1. |
| 3 | VIA | input | Channel A input on the VDD1 side; it must be held low when VDD1 is unpowered so that it does not back-power the device through its ESD clamp. |
| 4 | VIB | input | Channel B input on the VDD1 side; it must be held low when VDD1 is unpowered so that it does not back-power the device through its ESD clamp. |
| 5 | VOC | output | Channel C output on the VDD1 side; it is high-impedance while EN1 is low, and drives to the default level (low for the π142E60) when its input side is unpowered. |
| 6 | VOD | output | Channel D output on the VDD1 side; it is high-impedance while EN1 is low, and drives to the default level (low for the π142E60) when its input side is unpowered. |
| 7 | EN1 | input | Output-enable for VOC and VOD on the π142E6x variants; high or unconnected enables the outputs and low forces them to high-impedance (on π142E3x this pin is NC). |
| 8 | GND1 | power_in | Primary-side supply reference ground for VDD1. |
| 9 | GND2 | power_in | Secondary-side supply reference ground for VDD2. |
| 10 | EN2 | input | Output-enable for VOA and VOB on the π142E6x variants; high or unconnected enables the outputs and low forces them to high-impedance (on π142E3x this pin is NC). |
| 11 | VID | input | Channel D input on the VDD2 side; it must be held low when VDD2 is unpowered so that it does not back-power the device through its ESD clamp. |
| 12 | VIC | input | Channel C input on the VDD2 side; it must be held low when VDD2 is unpowered so that it does not back-power the device through its ESD clamp. |
| 13 | VOB | output | Channel B output on the VDD2 side; it is high-impedance while EN2 is low, and drives to the default level (low for the π142E60) when its input side is unpowered. |
| 14 | VOA | output | Channel A output on the VDD2 side; it is high-impedance while EN2 is low, and drives to the default level (low for the π142E60) when its input side is unpowered. |
| 15 | GND2 | power_in | Secondary-side supply reference ground for VDD2. |
| 16 | VDD2 | power_in | Secondary-side isolator supply; the datasheet gives a 3.0 V to 5.5 V supply range and a VDDx undervoltage threshold of 2.30 V to 2.95 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 供电电压 VDDx (recommended) | VDDx | 3 | 5.5 | V | 3 | ||
| 输入信号低电平 (VIL) | VIL | 0 | V | 4 | |||
| 输出高时输出电流 (IOH) | IOH | -6 | mA | 4 | |||
| 输出低时输出电流 (IOL) | IOL | 6 | mA | 4 | |||
| 通信速率 | 0 | 200 | Mbps | 4 | |||
| 结温 TJ | TJ | -40 | 150 | °C | 4 | ||
| 环境温度 TA | TA | -40 | 125 | °C | 4 | ||
| 供电电压 VDD1-GND1, VDD2-GND2 (absolute max) | VDD | -0.5 | 7 | V | 3 | ||
| 输入信号电压 VIA, VIB (absolute max) | VIA, VIB | -0.5 | V | 3 | |||
| 输出电压 VOA, VOB (absolute max) | VOA, VOB | -0.5 | V | 3 | |||
| 原边每通道输出平均电流 (absolute max) | IO1 | -10 | 10 | mA | 3 | ||
| 副边每通道输出平均电流 (absolute max) | IO2 | -10 | 10 | mA | 3 | ||
| 共模瞬变抗扰度 CMTI (absolute max) | CMTI | -200 | 200 | kV/µs | 3 | ||
| 存储温度范围 (absolute max) | TST | -65 | 150 | °C | 3 | ||
| 工作环境温度范围 (absolute max) | TA | -40 | 125 | °C | 3 | ||
| 最小脉冲宽度 PW | PW | 5 | ns | 在脉冲宽度失真(PWD)限制内 | 5 | ||
| 最大数据速率 | 200 | Mbps | 在脉冲宽度失真(PWD)限制内 | 5 | |||
| 传输延时 tpHL, tpLH (5V) | tpHL, tpLH | 12 | 16 | ns | 5VDC 供电时 | 5 | |
| 传输延时 tpHL, tpLH (3.3V) | tpHL, tpLH | 14 | 18.5 | ns | 3.3VDC 供电时 | 5 | |
| 脉宽失真 PWD (5V) | PWD | 0.3 | 3 | ns | 5VDC 供电时，tpHL 与 tpLH 最大差值 | 5 | |
| 脉宽失真 PWD (3.3V) | PWD | 0.4 | 3 | ns | 3.3VDC 供电时，tpHL 与 tpLH 最大差值 | 5 | |
| 不同器件间传输延时偏差 tPSK (5V) | tPSK | 2 | ns | 5VDC 供电时，相同温度、负载和电压下 | 5 | ||
| 不同器件间传输延时偏差 tPSK (3.3V) | tPSK | 2 | ns | 3.3VDC 供电时，相同温度、负载和电压下 | 6 | ||
| 通道间传输延时偏差 tCSK (5V) | tCSK | 0 | 1.8 | ns | 5VDC 供电时，单个器件中任何两个通道间 | 6 | |
| 通道间传输延时偏差 tCSK (3.3V) | tCSK | 0 | 2 | ns | 3.3VDC 供电时，单个器件中任何两个通道间 | 6 | |
| 输出信号上升/下降时间 tr/tf | tr/tf | 1.5 | ns | 参见图 10 | 6 | ||
| ESD (HBM 人体模型) | ESD | -8 | 8 | kV | HBM | 5 | |
| 输入信号低电平 (VOL 20µA) | VOL | 0 | 0.1 | V | 20 µA 输出电流 | 6 | |
| 低电平输出时电压 (VOL 2mA) | VOL | 0.1 | 0.2 | V | 2 mA 输出电流 | 6 | |
| 每通道输入电流 IIN | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ 信号电压 ≤ VDDX1 | 6 |
| VDDx1 欠电压阈值（电压上升） | VDDxUV+ | 2.45 | 2.75 | 2.95 | V | 6 | |
| VDDx1 欠电压阈值（电压下降） | VDDxUV- | 2.3 | 2.6 | 2.75 | V | 6 | |
| 禁用传播延迟，高电平到高阻抗输出 tPHZ (5V) | tPHZ | 20 | 41 | ns | 5VDC 供电 | 6 | |
| 禁用传播延迟，高电平到高阻抗输出 tPHZ (3.3V) | tPHZ | 24 | 50 | ns | 3.3VDC 供电 | 6 | |
| 禁用传播延迟，低电平到高阻抗输出 tPLZ (5V) | tPLZ | 20 | 41 | ns | 5VDC 供电 | 6 | |
| 禁用传播延迟，低电平到高阻抗输出 tPLZ (3.3V) | tPLZ | 24 | 50 | ns | 3.3VDC 供电 | 6 | |
| 使能传播延迟，高阻抗到高电平输出 tPZH (5V, π14xE60) | tPZH | 1.7 | 5.7 | us | 5VDC 供电, 适用于 π14xE60 | 6 | |
| 使能传播延迟，高阻抗到高电平输出 tPZH (3.3V, π14xE60) | tPZH | 1.1 | 4.4 | us | 3.3VDC 供电，适用于 π14xE60 | 6 | |
| 使能传播延迟，高阻抗到低电平输出 tPZL (5V, π14xE60) | tPZL | 12 | 25 | ns | 5VDC 供电, 适用于 π14xE60 | 6 | |
| 使能传播延迟，高阻抗到低电平输出 tPZL (3.3V, π14xE60) | tPZL | 16 | 33 | ns | 3.3VDC 供电，适用于 π14xE60 | 6 | |
| 静态供电电流 IDD1 (5V, EX0 低/EX1 高) | IDD1 (Q) | 0.89 | 1.12 | 1.46 | mA | 5VDC; π14xEx0 低电平 0V; π14xEx1 高电平 5V | 7 |
| 静态供电电流 IDD2 (5V, EX0 低/EX1 高) | IDD2 (Q) | 0.89 | 1.12 | 1.46 | mA | 5VDC; π14xEx1 高电平 5V | 8 |
| 静态供电电流 IDD1 (5V, EX0 高/EX1 低) | IDD1 (Q) | 1 | 1.25 | 1.63 | mA | 5VDC; π14xEx0 高电平 5V; π14xEx1 低电平 0V | 8 |
| 静态供电电流 IDD2 (5V, EX0 高/EX1 低) | IDD2 (Q) | 1 | 1.25 | 1.63 | mA | 5VDC; π14xEx1 低电平 0V | 8 |
| 静态供电电流 IDD1 (3.3V, EX0 低/EX1 高) | IDD1 (Q) | 0.86 | 1.08 | 1.41 | mA | 3.3VDC; π14xEx0 低电平 0V; π14xEx1 高电平 3.3V | 8 |
| 静态供电电流 IDD2 (3.3V, EX0 低/EX1 高) | IDD2 (Q) | 0.86 | 1.08 | 1.41 | mA | 3.3VDC; π14xEx1 高电平 3.3V | 8 |
| 静态供电电流 IDD1 (3.3V, EX0 高/EX1 低) | IDD1 (Q) | 0.89 | 1.12 | 1.45 | mA | 3.3VDC; π14xEx0 高电平 3.3V; π14xEx1 低电平 0V | 8 |
| 静态供电电流 IDD2 (3.3V, EX0 高/EX1 低) | IDD2 (Q) | 0.89 | 1.12 | 1.45 | mA | 3.3VDC; π14xEx1 低电平 0V | 8 |
| IC 结至空气热阻 (π14xE6x) | θJA | 45 | °C/W | 热电偶位于封装底面中心 | 9 |
CAD (KiCad official)
- Symbol:
π142E60 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
142e60-etched.step/142e60-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);142e60.step/142e60.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 2Pai Semi datasheet (20 pp, sha256
a0a54d435b6e297a, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# π142E60
**2Pai Semi** · Digital Isolators · SOIC-16-300mil
π142E60 from 2Pai Semi, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Primary-side isolator supply; the datasheet gives a 3.0 V to 5.5 V supply range and a VDDx undervoltage threshold of 2.30 V to 2.95 V. |
| 2 | GND1 | power_in | Primary-side supply reference ground for VDD1. |
| 3 | VIA | input | Channel A input on the VDD1 side; it must be held low when VDD1 is unpowered so that it does not back-power the device through its ESD clamp. |
| 4 | VIB | input | Channel B input on the VDD1 side; it must be held low when VDD1 is unpowered so that it does not back-power the device through its ESD clamp. |
| 5 | VOC | output | Channel C output on the VDD1 side; it is high-impedance while EN1 is low, and drives to the default level (low for the π142E60) when its input side is unpowered. |
| 6 | VOD | output | Channel D output on the VDD1 side; it is high-impedance while EN1 is low, and drives to the default level (low for the π142E60) when its input side is unpowered. |
| 7 | EN1 | input | Output-enable for VOC and VOD on the π142E6x variants; high or unconnected enables the outputs and low forces them to high-impedance (on π142E3x this pin is NC). |
| 8 | GND1 | power_in | Primary-side supply reference ground for VDD1. |
| 9 | GND2 | power_in | Secondary-side supply reference ground for VDD2. |
| 10 | EN2 | input | Output-enable for VOA and VOB on the π142E6x variants; high or unconnected enables the outputs and low forces them to high-impedance (on π142E3x this pin is NC). |
| 11 | VID | input | Channel D input on the VDD2 side; it must be held low when VDD2 is unpowered so that it does not back-power the device through its ESD clamp. |
| 12 | VIC | input | Channel C input on the VDD2 side; it must be held low when VDD2 is unpowered so that it does not back-power the device through its ESD clamp. |
| 13 | VOB | output | Channel B output on the VDD2 side; it is high-impedance while EN2 is low, and drives to the default level (low for the π142E60) when its input side is unpowered. |
| 14 | VOA | output | Channel A output on the VDD2 side; it is high-impedance while EN2 is low, and drives to the default level (low for the π142E60) when its input side is unpowered. |
| 15 | GND2 | power_in | Secondary-side supply reference ground for VDD2. |
| 16 | VDD2 | power_in | Secondary-side isolator supply; the datasheet gives a 3.0 V to 5.5 V supply range and a VDDx undervoltage threshold of 2.30 V to 2.95 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 供电电压 VDDx (recommended) | VDDx | 3 | | 5.5 | V | | 3 |
| 输入信号低电平 (VIL) | VIL | 0 | | | V | | 4 |
| 输出高时输出电流 (IOH) | IOH | -6 | | | mA | | 4 |
| 输出低时输出电流 (IOL) | IOL | | | 6 | mA | | 4 |
| 通信速率 | | 0 | | 200 | Mbps | | 4 |
| 结温 TJ | TJ | -40 | | 150 | °C | | 4 |
| 环境温度 TA | TA | -40 | | 125 | °C | | 4 |
| 供电电压 VDD1-GND1, VDD2-GND2 (absolute max) | VDD | -0.5 | | 7 | V | | 3 |
| 输入信号电压 VIA, VIB (absolute max) | VIA, VIB | -0.5 | | | V | | 3 |
| 输出电压 VOA, VOB (absolute max) | VOA, VOB | -0.5 | | | V | | 3 |
| 原边每通道输出平均电流 (absolute max) | IO1 | -10 | | 10 | mA | | 3 |
| 副边每通道输出平均电流 (absolute max) | IO2 | -10 | | 10 | mA | | 3 |
| 共模瞬变抗扰度 CMTI (absolute max) | CMTI | -200 | | 200 | kV/µs | | 3 |
| 存储温度范围 (absolute max) | TST | -65 | | 150 | °C | | 3 |
| 工作环境温度范围 (absolute max) | TA | -40 | | 125 | °C | | 3 |
| 最小脉冲宽度 PW | PW | 5 | | | ns | 在脉冲宽度失真(PWD)限制内 | 5 |
| 最大数据速率 | | | | 200 | Mbps | 在脉冲宽度失真(PWD)限制内 | 5 |
| 传输延时 tpHL, tpLH (5V) | tpHL, tpLH | 12 | | 16 | ns | 5VDC 供电时 | 5 |
| 传输延时 tpHL, tpLH (3.3V) | tpHL, tpLH | 14 | | 18.5 | ns | 3.3VDC 供电时 | 5 |
| 脉宽失真 PWD (5V) | PWD | 0.3 | | 3 | ns | 5VDC 供电时，tpHL 与 tpLH 最大差值 | 5 |
| 脉宽失真 PWD (3.3V) | PWD | 0.4 | | 3 | ns | 3.3VDC 供电时，tpHL 与 tpLH 最大差值 | 5 |
| 不同器件间传输延时偏差 tPSK (5V) | tPSK | | | 2 | ns | 5VDC 供电时，相同温度、负载和电压下 | 5 |
| 不同器件间传输延时偏差 tPSK (3.3V) | tPSK | | | 2 | ns | 3.3VDC 供电时，相同温度、负载和电压下 | 6 |
| 通道间传输延时偏差 tCSK (5V) | tCSK | 0 | | 1.8 | ns | 5VDC 供电时，单个器件中任何两个通道间 | 6 |
| 通道间传输延时偏差 tCSK (3.3V) | tCSK | 0 | | 2 | ns | 3.3VDC 供电时，单个器件中任何两个通道间 | 6 |
| 输出信号上升/下降时间 tr/tf | tr/tf | | | 1.5 | ns | 参见图 10 | 6 |
| ESD (HBM 人体模型) | ESD | -8 | | 8 | kV | HBM | 5 |
| 输入信号低电平 (VOL 20µA) | VOL | 0 | | 0.1 | V | 20 µA 输出电流 | 6 |
| 低电平输出时电压 (VOL 2mA) | VOL | 0.1 | | 0.2 | V | 2 mA 输出电流 | 6 |
| 每通道输入电流 IIN | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ 信号电压 ≤ VDDX1 | 6 |
| VDDx1 欠电压阈值（电压上升） | VDDxUV+ | 2.45 | 2.75 | 2.95 | V | | 6 |
| VDDx1 欠电压阈值（电压下降） | VDDxUV- | 2.3 | 2.6 | 2.75 | V | | 6 |
| 禁用传播延迟，高电平到高阻抗输出 tPHZ (5V) | tPHZ | 20 | | 41 | ns | 5VDC 供电 | 6 |
| 禁用传播延迟，高电平到高阻抗输出 tPHZ (3.3V) | tPHZ | 24 | | 50 | ns | 3.3VDC 供电 | 6 |
| 禁用传播延迟，低电平到高阻抗输出 tPLZ (5V) | tPLZ | 20 | | 41 | ns | 5VDC 供电 | 6 |
| 禁用传播延迟，低电平到高阻抗输出 tPLZ (3.3V) | tPLZ | 24 | | 50 | ns | 3.3VDC 供电 | 6 |
| 使能传播延迟，高阻抗到高电平输出 tPZH (5V, π14xE60) | tPZH | 1.7 | | 5.7 | us | 5VDC 供电, 适用于 π14xE60 | 6 |
| 使能传播延迟，高阻抗到高电平输出 tPZH (3.3V, π14xE60) | tPZH | 1.1 | | 4.4 | us | 3.3VDC 供电，适用于 π14xE60 | 6 |
| 使能传播延迟，高阻抗到低电平输出 tPZL (5V, π14xE60) | tPZL | 12 | | 25 | ns | 5VDC 供电, 适用于 π14xE60 | 6 |
| 使能传播延迟，高阻抗到低电平输出 tPZL (3.3V, π14xE60) | tPZL | 16 | | 33 | ns | 3.3VDC 供电，适用于 π14xE60 | 6 |
| 静态供电电流 IDD1 (5V, EX0 低/EX1 高) | IDD1 (Q) | 0.89 | 1.12 | 1.46 | mA | 5VDC; π14xEx0 低电平 0V; π14xEx1 高电平 5V | 7 |
| 静态供电电流 IDD2 (5V, EX0 低/EX1 高) | IDD2 (Q) | 0.89 | 1.12 | 1.46 | mA | 5VDC; π14xEx1 高电平 5V | 8 |
| 静态供电电流 IDD1 (5V, EX0 高/EX1 低) | IDD1 (Q) | 1 | 1.25 | 1.63 | mA | 5VDC; π14xEx0 高电平 5V; π14xEx1 低电平 0V | 8 |
| 静态供电电流 IDD2 (5V, EX0 高/EX1 低) | IDD2 (Q) | 1 | 1.25 | 1.63 | mA | 5VDC; π14xEx1 低电平 0V | 8 |
| 静态供电电流 IDD1 (3.3V, EX0 低/EX1 高) | IDD1 (Q) | 0.86 | 1.08 | 1.41 | mA | 3.3VDC; π14xEx0 低电平 0V; π14xEx1 高电平 3.3V | 8 |
| 静态供电电流 IDD2 (3.3V, EX0 低/EX1 高) | IDD2 (Q) | 0.86 | 1.08 | 1.41 | mA | 3.3VDC; π14xEx1 高电平 3.3V | 8 |
| 静态供电电流 IDD1 (3.3V, EX0 高/EX1 低) | IDD1 (Q) | 0.89 | 1.12 | 1.45 | mA | 3.3VDC; π14xEx0 高电平 3.3V; π14xEx1 低电平 0V | 8 |
| 静态供电电流 IDD2 (3.3V, EX0 高/EX1 低) | IDD2 (Q) | 0.89 | 1.12 | 1.45 | mA | 3.3VDC; π14xEx1 低电平 0V | 8 |
| IC 结至空气热阻 (π14xE6x) | θJA | | 45 | | °C/W | 热电偶位于封装底面中心 | 9 |
## CAD (KiCad official)
- Symbol: `π142E60`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files: `142e60-etched.step` / `142e60-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `142e60.step` / `142e60.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [2Pai Semi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590903221731356672) (20 pp, sha256 `a0a54d435b6e297a`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/142e60-datasheet.pdf)