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π141U31
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2Pai Semi Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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π141U31
2Pai Semi · Digital Isolators · SOIC-16
π141U31 from 2Pai Semi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, specified at 3 V to 5.5 V in the recommended operating conditions. |
| 2 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 3 | VIA | input | Logic input A; high-level input must be at least 0.7×VDD1 and low-level input at most 0.3×VDD1. |
| 4 | VIB | input | Logic input B; high-level input must be at least 0.7×VDD1 and low-level input at most 0.3×VDD1. |
| 5 | VIC | input | Logic input C; high-level input must be at least 0.7×VDD1 and low-level input at most 0.3×VDD1. |
| 6 | VOD | output | Logic output D as printed in the pin table; output high-level current limited to −6 mA and low-level current to 6 mA. |
| 7 | NC/EN1 | unconnected | No connect for π141U3X; on the π141U6X variant this pin is output enable 1 (side-1 outputs high-impedance when EN1 is low). |
| 8 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 9 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 10 | NC/EN2 | unconnected | No connect for π141U3X; on the π141U6X variant this pin is output enable 2 (side-2 outputs high-impedance when EN2 is low). |
| 11 | VID | input | Logic input D as printed in the pin table; high-level input must be at least 0.7×VDD2 and low-level input at most 0.3×VDD2 for side 2 operation. |
| 12 | VOC | output | Logic output C; output high-level current limited to −6 mA and low-level current to 6 mA. |
| 13 | VOB | output | Logic output B; output high-level current limited to −6 mA and low-level current to 6 mA. |
| 14 | VOA | output | Logic output A; output high-level current limited to −6 mA and low-level current to 6 mA. |
| 15 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 16 | VDD2 | power_in | Supply voltage for isolator side 2, specified at 3 V to 5.5 V in the recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VDDx) | VDDx | 3 | 5.5 | V | 4 | ||
| Low Level Input Signal Voltage | VIL | 0 | V | 4 | |||
| Maximum Data Rate | 0 | 150 | Kbps | 4 | |||
| Junction Temperature | TJ | -40 | 150 | °C | 4 | ||
| Ambient Operating Temperature | TA | -40 | 125 | °C | 4 | ||
| Supply Voltages (VDD1-GND1, VDD2-GND2) | -0.5 | 7 | V | TA = 25°C | 3 | ||
| Input Voltages (VIA, VIB) | -0.5 | V | TA = 25°C; max printed as VDDx + 0.5 V | 3 | |||
| Output Voltages (VOA, VOB) | -0.5 | V | TA = 25°C; max printed as VDDx + 0.5 V | 3 | |||
| Average Output Current per Pin, Side 1 | IO1 | -10 | 10 | mA | TA = 25°C | 3 | |
| Average Output Current per Pin, Side 2 | IO2 | -10 | 10 | mA | TA = 25°C | 3 | |
| Common-Mode Transients Immunity | -150 | 150 | kV/µs | TA = 25°C | 3 | ||
| Storage Temperature Range | TST | -65 | 150 | °C | TA = 25°C | 3 | |
| Ambient Operating Temperature Range | TA | -40 | 125 | °C | TA = 25°C | 3 | |
| Minimum Pulse Width | PW | 6.5 | us | Within pulse width distortion (PWD) limit | 5 | ||
| Maximum Data Rate | 150 | Kbps | Within PWD limit | 5 | |||
| Propagation Delay Time | tpHL, tpLH | 3 | 4.5 | us | 50% input to 50% output, 5VDC supply | 5 | |
| Propagation Delay Time | tpHL, tpLH | 3.2 | 4.8 | us | 50% input to 50% output, 3.3VDC supply | 5 | |
| Pulse Width Distortion | PWD | 0 | 0.02 | 0.2 | us | /tpHL - tpLH/, 5VDC supply | 5 |
| Part to Part Propagation Delay Skew | tPSK | 0.3 | us | Between any two devices, same temperature, load and voltage, 5VDC supply | 5 | ||
| Channel to Channel Propagation Delay Skew | tCSK | 0 | 0.2 | us | Between any two output channels in one device, 5VDC supply | 5 | |
| Output Signal Rise/Fall Time | tr/tf | 1.5 | ns | 10% to 90%, signal terminated 50Ω | 5 | ||
| Common-Mode Transient Immunity | CMTI | 100 | 150 | kV/µs | VIN = VDDx or 0V, VCM = 1000 V | 5 | |
| ESD Human Body Model | ESD | -8 | 8 | kV | HBM, all pins | 5 | |
| Low Level Output Voltage | VOL | 0 | 0.1 | V | 20 µA output current | 5 | |
| Low Level Output Voltage | VOL | 0.1 | 0.2 | V | 2 mA output current | 5 | |
| Input Current per Signal Channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ Signal voltage ≤ VDDX1 | 5 |
| VDDx1 Undervoltage Rising Threshold | VDDxUV+ | 2.45 | 2.65 | 2.9 | V | 6 | |
| VDDx1 Undervoltage Falling Threshold | VDDxUV− | 2.3 | 2.5 | 2.75 | V | 6 | |
| π141Uxx Quiescent Supply Current IDD1(Q) | IDD1 (Q) | 584 | 731 | 950 | µA | 5VDC supply; 0V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD2(Q) | IDD2 (Q) | 1139 | 1424 | 1851 | µA | 5VDC supply; 0V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD1(Q) | IDD1 (Q) | 475 | 594 | 772 | µA | 5VDC supply; 5V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD2(Q) | IDD2 (Q) | 1182 | 1477 | 1920 | µA | 5VDC supply; 5V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD1(Q) | IDD1 (Q) | 517 | 647 | 840 | µA | 3.3VDC supply; 0V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD2(Q) | IDD2 (Q) | 1101 | 1376 | 1789 | µA | 3.3VDC supply; 0V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD1(Q) | IDD1 (Q) | 469 | 587 | 762 | µA | 3.3VDC supply; 3.3V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD2(Q) | IDD2 (Q) | 1168 | 1460 | 1898 | µA | 3.3VDC supply; 3.3V input signal | 6 |
| π141Uxx Total Supply Current IDD1 | IDD1 | 0.66 | 0.98 | mA | 2 Kbps; 5VDC supply; CL = 0 pF | 6 | |
| π141Uxx Total Supply Current IDD1 | IDD1 | 0.66 | 0.99 | mA | 50 Kbps; 5VDC supply; CL = 0 pF | 6 | |
| π141Uxx Total Supply Current IDD1 | IDD1 | 0.67 | 1 | mA | 150 Kbps; 5VDC supply; CL = 0 pF | 6 | |
| π141Uxx Total Supply Current IDD2 | IDD2 | 1.45 | 2.18 | mA | 2 Kbps; 5VDC supply; CL = 0 pF | 7 | |
| π141Uxx Total Supply Current IDD2 | IDD2 | 1.46 | 2.19 | mA | 50 Kbps; 5VDC supply; CL = 0 pF | 7 | |
| π141Uxx Total Supply Current IDD2 | IDD2 | 1.48 | 2.22 | mA | 150 Kbps; 5VDC supply; CL = 0 pF | 7 | |
| π141Uxx Total Supply Current IDD1 | IDD1 | 0.61 | 0.91 | mA | 2 Kbps; 3.3VDC supply; CL = 0 pF | 7 | |
| π141Uxx Total Supply Current IDD1 | IDD1 | 0.61 | 0.92 | mA | 50 Kbps; 3.3VDC supply; CL = 0 pF | 7 | |
| π141Uxx Total Supply Current IDD2 | IDD2 | 1.42 | 2.13 | mA | 2 Kbps; 3.3VDC supply; CL = 0 pF | 7 | |
| π141Uxx Total Supply Current IDD2 | IDD2 | 1.43 | 2.15 | mA | 150 Kbps; 3.3VDC supply; CL = 0 pF | 7 | |
| Hysteresis VDDx1 Undervoltage | VDDxUVH | 0.15 | V | 6 | |||
| IC Junction to Ambient Thermal Resistance | θJA | 100 | °C/W | Thermocouple located at center of package underside (π14xU3x) | 7 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN V VDE V 0884-10, each π140U3x/π141U3x/π142U3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial discharge detection limit = 5 pC); each π14 | 8 |
CAD (KiCad official)
- Symbol:
π141U31 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
141u31-etched.step/141u31-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);141u31.step/141u31.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 2Pai Semi datasheet (17 pp, sha256
a0b32e720baaca62, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# π141U31
**2Pai Semi** · Digital Isolators · SOIC-16
π141U31 from 2Pai Semi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, specified at 3 V to 5.5 V in the recommended operating conditions. |
| 2 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 3 | VIA | input | Logic input A; high-level input must be at least 0.7×VDD1 and low-level input at most 0.3×VDD1. |
| 4 | VIB | input | Logic input B; high-level input must be at least 0.7×VDD1 and low-level input at most 0.3×VDD1. |
| 5 | VIC | input | Logic input C; high-level input must be at least 0.7×VDD1 and low-level input at most 0.3×VDD1. |
| 6 | VOD | output | Logic output D as printed in the pin table; output high-level current limited to −6 mA and low-level current to 6 mA. |
| 7 | NC/EN1 | unconnected | No connect for π141U3X; on the π141U6X variant this pin is output enable 1 (side-1 outputs high-impedance when EN1 is low). |
| 8 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 9 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 10 | NC/EN2 | unconnected | No connect for π141U3X; on the π141U6X variant this pin is output enable 2 (side-2 outputs high-impedance when EN2 is low). |
| 11 | VID | input | Logic input D as printed in the pin table; high-level input must be at least 0.7×VDD2 and low-level input at most 0.3×VDD2 for side 2 operation. |
| 12 | VOC | output | Logic output C; output high-level current limited to −6 mA and low-level current to 6 mA. |
| 13 | VOB | output | Logic output B; output high-level current limited to −6 mA and low-level current to 6 mA. |
| 14 | VOA | output | Logic output A; output high-level current limited to −6 mA and low-level current to 6 mA. |
| 15 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 16 | VDD2 | power_in | Supply voltage for isolator side 2, specified at 3 V to 5.5 V in the recommended operating conditions. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VDDx) | VDDx | 3 | | 5.5 | V | | 4 |
| Low Level Input Signal Voltage | VIL | 0 | | | V | | 4 |
| Maximum Data Rate | | 0 | | 150 | Kbps | | 4 |
| Junction Temperature | TJ | -40 | | 150 | °C | | 4 |
| Ambient Operating Temperature | TA | -40 | | 125 | °C | | 4 |
| Supply Voltages (VDD1-GND1, VDD2-GND2) | | -0.5 | | 7 | V | TA = 25°C | 3 |
| Input Voltages (VIA, VIB) | | -0.5 | | | V | TA = 25°C; max printed as VDDx + 0.5 V | 3 |
| Output Voltages (VOA, VOB) | | -0.5 | | | V | TA = 25°C; max printed as VDDx + 0.5 V | 3 |
| Average Output Current per Pin, Side 1 | IO1 | -10 | | 10 | mA | TA = 25°C | 3 |
| Average Output Current per Pin, Side 2 | IO2 | -10 | | 10 | mA | TA = 25°C | 3 |
| Common-Mode Transients Immunity | | -150 | | 150 | kV/µs | TA = 25°C | 3 |
| Storage Temperature Range | TST | -65 | | 150 | °C | TA = 25°C | 3 |
| Ambient Operating Temperature Range | TA | -40 | | 125 | °C | TA = 25°C | 3 |
| Minimum Pulse Width | PW | 6.5 | | | us | Within pulse width distortion (PWD) limit | 5 |
| Maximum Data Rate | | | | 150 | Kbps | Within PWD limit | 5 |
| Propagation Delay Time | tpHL, tpLH | 3 | | 4.5 | us | 50% input to 50% output, 5VDC supply | 5 |
| Propagation Delay Time | tpHL, tpLH | 3.2 | | 4.8 | us | 50% input to 50% output, 3.3VDC supply | 5 |
| Pulse Width Distortion | PWD | 0 | 0.02 | 0.2 | us | /tpHL - tpLH/, 5VDC supply | 5 |
| Part to Part Propagation Delay Skew | tPSK | | | 0.3 | us | Between any two devices, same temperature, load and voltage, 5VDC supply | 5 |
| Channel to Channel Propagation Delay Skew | tCSK | 0 | | 0.2 | us | Between any two output channels in one device, 5VDC supply | 5 |
| Output Signal Rise/Fall Time | tr/tf | | | 1.5 | ns | 10% to 90%, signal terminated 50Ω | 5 |
| Common-Mode Transient Immunity | CMTI | 100 | 150 | | kV/µs | VIN = VDDx or 0V, VCM = 1000 V | 5 |
| ESD Human Body Model | ESD | -8 | | 8 | kV | HBM, all pins | 5 |
| Low Level Output Voltage | VOL | 0 | | 0.1 | V | 20 µA output current | 5 |
| Low Level Output Voltage | VOL | 0.1 | | 0.2 | V | 2 mA output current | 5 |
| Input Current per Signal Channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ Signal voltage ≤ VDDX1 | 5 |
| VDDx1 Undervoltage Rising Threshold | VDDxUV+ | 2.45 | 2.65 | 2.9 | V | | 6 |
| VDDx1 Undervoltage Falling Threshold | VDDxUV− | 2.3 | 2.5 | 2.75 | V | | 6 |
| π141Uxx Quiescent Supply Current IDD1(Q) | IDD1 (Q) | 584 | 731 | 950 | µA | 5VDC supply; 0V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD2(Q) | IDD2 (Q) | 1139 | 1424 | 1851 | µA | 5VDC supply; 0V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD1(Q) | IDD1 (Q) | 475 | 594 | 772 | µA | 5VDC supply; 5V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD2(Q) | IDD2 (Q) | 1182 | 1477 | 1920 | µA | 5VDC supply; 5V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD1(Q) | IDD1 (Q) | 517 | 647 | 840 | µA | 3.3VDC supply; 0V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD2(Q) | IDD2 (Q) | 1101 | 1376 | 1789 | µA | 3.3VDC supply; 0V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD1(Q) | IDD1 (Q) | 469 | 587 | 762 | µA | 3.3VDC supply; 3.3V input signal | 6 |
| π141Uxx Quiescent Supply Current IDD2(Q) | IDD2 (Q) | 1168 | 1460 | 1898 | µA | 3.3VDC supply; 3.3V input signal | 6 |
| π141Uxx Total Supply Current IDD1 | IDD1 | | 0.66 | 0.98 | mA | 2 Kbps; 5VDC supply; CL = 0 pF | 6 |
| π141Uxx Total Supply Current IDD1 | IDD1 | | 0.66 | 0.99 | mA | 50 Kbps; 5VDC supply; CL = 0 pF | 6 |
| π141Uxx Total Supply Current IDD1 | IDD1 | | 0.67 | 1 | mA | 150 Kbps; 5VDC supply; CL = 0 pF | 6 |
| π141Uxx Total Supply Current IDD2 | IDD2 | | 1.45 | 2.18 | mA | 2 Kbps; 5VDC supply; CL = 0 pF | 7 |
| π141Uxx Total Supply Current IDD2 | IDD2 | | 1.46 | 2.19 | mA | 50 Kbps; 5VDC supply; CL = 0 pF | 7 |
| π141Uxx Total Supply Current IDD2 | IDD2 | | 1.48 | 2.22 | mA | 150 Kbps; 5VDC supply; CL = 0 pF | 7 |
| π141Uxx Total Supply Current IDD1 | IDD1 | | 0.61 | 0.91 | mA | 2 Kbps; 3.3VDC supply; CL = 0 pF | 7 |
| π141Uxx Total Supply Current IDD1 | IDD1 | | 0.61 | 0.92 | mA | 50 Kbps; 3.3VDC supply; CL = 0 pF | 7 |
| π141Uxx Total Supply Current IDD2 | IDD2 | | 1.42 | 2.13 | mA | 2 Kbps; 3.3VDC supply; CL = 0 pF | 7 |
| π141Uxx Total Supply Current IDD2 | IDD2 | | 1.43 | 2.15 | mA | 150 Kbps; 3.3VDC supply; CL = 0 pF | 7 |
| Hysteresis VDDx1 Undervoltage | VDDxUVH | | 0.15 | | V | | 6 |
| IC Junction to Ambient Thermal Resistance | θJA | | 100 | | °C/W | Thermocouple located at center of package underside (π14xU3x) | 7 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | | In accordance with DIN V VDE V 0884-10, each π140U3x/π141U3x/π142U3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial discharge detection limit = 5 pC); each π14 | 8 |
## CAD (KiCad official)
- Symbol: `π141U31`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `141u31-etched.step` / `141u31-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `141u31.step` / `141u31.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [2Pai Semi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885113064710144) (17 pp, sha256 `a0b32e720baaca62`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/141u31-datasheet.pdf)