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π141M31

Public Made by Adom

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2Pai Semi Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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π141M31

2Pai Semi · Digital Isolators · SOIC-16

π141M31 from 2Pai Semi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, specified at 3 V to 5.5 V in the recommended operating conditions.
2 GND1 power_in Ground 1, the ground reference for isolator side 1.
3 VIA input Logic input A on side 1; high level input must be at least 0.7VDDx and low level at most 0.3VDDx.
4 VIB input Logic input B on side 1; high level input must be at least 0.7VDDx and low level at most 0.3VDDx.
5 VIC input Logic input C on side 1; high level input must be at least 0.7VDDx and low level at most 0.3VDDx.
6 VOD output Logic output D on side 1; high-level output current limited to -6 mA and low-level output current to 6 mA.
7 NC unconnected No connect for π141M3X (this package variant); the pin is not used and is labeled NC/EN1 for the π141M6X variant.
8 GND1 power_in Ground 1, the ground reference for isolator side 1.
9 GND2 power_in Ground 2, the ground reference for isolator side 2.
10 NC unconnected No connect for π141M3X (this package variant); the pin is labeled NC/EN2 and serves as output enable 2 only on π141M6X.
11 VID input Logic input D on side 2; high level input must be at least 0.7VDDx and low level at most 0.3VDDx.
12 VOC output Logic output C on side 2; high-level output current limited to -6 mA and low-level output current to 6 mA.
13 VOB output Logic output B on side 2; high-level output current limited to -6 mA and low-level output current to 6 mA.
14 VOA output Logic output A on side 2; high-level output current limited to -6 mA and low-level output current to 6 mA.
15 GND2 power_in Ground 2, the ground reference for isolator side 2.
16 VDD2 power_in Supply voltage for isolator side 2, specified at 3 V to 5.5 V in the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer 2Pai Semi
Package SOIC-16
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltages (VDD1-GND1, VDD2-GND2) -0.5 7 V 3
Input Voltages (VIA, VIB) VIA, VIB -0.5 V 3
Output Voltages (VOA, VOB) VOA, VOB -0.5 V 3
Average Output Current per Pin, Side 1 IO1 -10 10 mA 3
Average Output Current per Pin, Side 2 IO2 -10 10 mA 3
Common-Mode Transients Immunity -150 150 kV/µs 3
Storage Temperature (TST) Range TST -65 150 °C 3
Ambient Operating Temperature (TA) Range TA -40 125 °C 3
Supply Voltage VDDx 3 5.5 V 4
Low Level Input Signal Voltage VIL 0 V 4
High Level Output Current IOH -6 mA 4
Low Level Output Current IOL 6 mA 4
Maximum Data Rate 0 10 Mbps 4
Junction Temperature TJ -40 150 °C 4
Ambient Operating Temperature TA -40 125 °C 4
Minimum Pulse Width PW 100 ns Within pulse width distortion (PWD) limit 5
Maximum Data Rate 10 Mbps Within PWD limit 5
Propagation Delay Time tpHL, tpLH 5.5 8 12.5 ns 50% input to 50% output signal, 50% @ 5VDC supply 5
Propagation Delay Time tpHL, tpLH 6.5 9 13.5 ns @ 3.3VDC supply 5
Pulse Width Distortion PWD 0 0.3 0.8 ns /tpHL - tpLH/ @ 5VDC supply 5
Part to Part Propagation Delay Skew tPSK 1 ns Same temperature, load and voltage @ 5VDC supply 5
Channel to Channel Propagation Delay Skew tCSK 0 1 ns Between output channels in one device @ 5VDC supply 5
Channel to Channel Propagation Delay Skew tCSK 0 0.8 ns @ 3.3VDC supply 5
Output Signal Rise/Fall Time tr/tf 1.5 ns 10% to 90% signal terminated 50 5
ESD (HBM - Human Body Model) ESD -8 8 kV HBM, all pins 5
Low Level Output Voltage VOL 0 0.1 V 20 µA output current 6
Low Level Output Voltage VOL 0.1 0.2 V 2 mA output current 6
Input Current per Signal Channel IIN -10 0.5 10 µA 0 V ≤ Signal voltage ≤ VDDX1 6
VDDx1 Undervoltage Rising Threshold VDDxUV+ 2.45 2.65 2.9 V 6
VDDx1 Undervoltage Falling Threshold VDDxUV− 2.3 2.5 2.75 V 6
Quiescent Supply Current IDD1 (Q) IDD1 (Q) 483 604 785 µA @ 5VDC Supply; 0V Input signal 6
Quiescent Supply Current IDD2 (Q) IDD2 (Q) 1200 1500 1950 µA @ 5VDC Supply; 0V Input signal 6
Quiescent Supply Current IDD1 (Q) IDD1 (Q) 594 742 965 µA @ 5VDC Supply; 5V Input signal 6
Quiescent Supply Current IDD2 (Q) IDD2 (Q) 1174 1468 1908 µA @ 5VDC Supply; 5V Input signal 6
Quiescent Supply Current IDD1 (Q) IDD1 (Q) 478 597 776 µA @ 3.3VDC Supply; 0V Input signal 6
Quiescent Supply Current IDD2 (Q) IDD2 (Q) 1186 1483 1928 µA @ 3.3VDC Supply; 0V Input signal 6
Quiescent Supply Current IDD1 (Q) IDD1 (Q) 524 655 852 µA @ 3.3VDC Supply; 3.3V Input signal 6
Quiescent Supply Current IDD2 (Q) IDD2 (Q) 1117 1396 1815 µA @ 3.3VDC Supply; 3.3V Input signal 6
Total Supply Current IDD1 at 150 kbps IDD1 0.68 1.02 mA @ 5VDC Supply; 150 Kbps; CL = 0 pF 7
Total Supply Current IDD1 at 1 Mbps IDD1 0.73 1.1 mA @ 5VDC Supply; 1 Mbps; CL = 0 pF 7
Total Supply Current IDD1 at 10 Mbps IDD1 1.21 1.82 mA @ 5VDC Supply; 10 Mbps; CL = 0 pF 7
Total Supply Current IDD2 at 150 kbps IDD2 1.49 2.24 mA @ 5VDC Supply; 150 Kbps; CL = 0 pF 7
Total Supply Current IDD2 at 1 Mbps IDD2 1.6 2.4 mA @ 5VDC Supply; 1 Mbps; CL = 0 pF 7
Total Supply Current IDD2 at 10 Mbps IDD2 2.73 4.1 mA @ 5VDC Supply; 10 Mbps; CL = 0 pF 7
Total Supply Current IDD1 at 150 kbps IDD1 0.63 0.95 mA @ 3.3VDC Supply; 150 Kbps; CL = 0 pF 7
Total Supply Current IDD1 at 1 Mbps IDD1 0.66 0.99 mA @ 3.3VDC Supply; 1 Mbps; CL = 0 pF 7
Total Supply Current IDD1 at 10 Mbps IDD1 0.95 1.43 mA @ 3.3VDC Supply; 10 Mbps; CL = 0 pF 7
Total Supply Current IDD2 at 150 kbps IDD2 1.45 2.18 mA @ 3.3VDC Supply; 150 Kbps; CL = 0 pF 7
Total Supply Current IDD2 at 1 Mbps IDD2 1.51 2.27 mA @ 3.3VDC Supply; 1 Mbps; CL = 0 pF 7
Total Supply Current IDD2 at 10 Mbps IDD2 2.2 3.3 mA @ 3.3VDC Supply; 10 Mbps; CL = 0 pF 7
IC Junction to Ambient Thermal Resistance (π14xM3x) θJA 100 °C/W Thermocouple located at center of package underside 7

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN V VDE V 0884-10, each π140M3x/π141M3x/π142M3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial discharge detection limit = 5 pC); each π14 8

CAD (KiCad official)

  • Symbol: π141M31
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 141m31-etched.step / 141m31-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 141m31.step / 141m31.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 2Pai Semi datasheet (17 pp, sha256 4971bc94a2e73c2a, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF