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π141E61
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2Pai Semi Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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π141E61
2Pai Semi · Digital Isolators · SOIC-16-300mil
π141E61 from 2Pai Semi, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, operating from 3 V to 5.5 V. |
| 2 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 3 | VIA | input | Logic input A; high-level input needs at least 0.7×VDDx1 and low-level input at most 0.3×VDDx1. |
| 4 | VIB | input | Logic input B; high-level input needs at least 0.7×VDDx1 and low-level input at most 0.3×VDDx1. |
| 5 | VIC | input | Logic input C; high-level input needs at least 0.7×VDDx1 and low-level input at most 0.3×VDDx1. |
| 6 | VOD | output | Logic output D on side 1; the datasheet limits output current to IOH −6 mA and IOL 6 mA. |
| 7 | NC/EN1 | input | Output enable 1 for π141E6X: side-1 outputs are enabled when EN1 is high or open and are high-impedance when EN1 is low (no connect on π141E3X). |
| 8 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 9 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 10 | NC/EN2 | input | Output enable 2 for π141E6X: side-2 outputs are enabled when EN2 is high or open and are high-impedance when EN2 is low (no connect on π141E3X). |
| 11 | VID | input | Logic input D; high-level input needs at least 0.7×VDDx2 and low-level input at most 0.3×VDDx2. |
| 12 | VOC | output | Logic output C on side 2; the datasheet limits output current to IOH −6 mA and IOL 6 mA. |
| 13 | VOB | output | Logic output B on side 2; the datasheet limits output current to IOH −6 mA and IOL 6 mA. |
| 14 | VOA | output | Logic output A on side 2; the datasheet limits output current to IOH −6 mA and IOL 6 mA. |
| 15 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 16 | VDD2 | power_in | Supply voltage for isolator side 2, operating from 3 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDDx | 3 | 5.5 | V | 4 | ||
| Low Level Input Signal Voltage | VIL | 0 | V | 4 | |||
| High Level Output Current | IOH | -6 | mA | 4 | |||
| Low Level Output Current | IOL | 6 | mA | 4 | |||
| Data Rate | 0 | 200 | Mbps | 4 | |||
| Junction Temperature | TJ | -40 | 150 | °C | 4 | ||
| Ambient Operating Temperature | TA | -40 | 125 | °C | 4 | ||
| Supply Voltages (VDD1-GND1, VDD2-GND2) | -0.5 | 7 | V | 3 | |||
| Input Voltages (VIA, VIB) | -0.5 | V | 3 | ||||
| Output Voltages (VOA, VOB) | -0.5 | V | 3 | ||||
| Average Output Current per Pin, Side 1 | IO1 | -10 | 10 | mA | 3 | ||
| Average Output Current per Pin, Side 2 | IO2 | -10 | 10 | mA | 3 | ||
| Common-Mode Transients Immunity | -200 | 200 | kV/µs | 3 | |||
| Storage Temperature Range | TST | -65 | 150 | °C | 3 | ||
| Ambient Operating Temperature Range | TA | -40 | 125 | °C | 3 | ||
| Minimum Pulse Width | PW | 5 | ns | Within pulse width distortion (PWD) limit | 5 | ||
| Maximum Data Rate | 200 | Mbps | Within PWD limit | 5 | |||
| Propagation Delay Time, 5VDC supply | tpHL, tpLH | 12 | 16 | ns | 5VDC supply | 5 | |
| Propagation Delay Time, 3.3VDC supply | tpHL, tpLH | 14 | 18.5 | ns | 3.3VDC supply | 5 | |
| Pulse Width Distortion, 5VDC supply | PWD | 0.3 | 3 | ns | The max different time between tpHL and tpLH @ 5VDC supply. And the value is / tpHL - tpLH / | 5 | |
| Quiescent Supply Current, side 1 (5VDC, VI=0V) | IDD1 (Q) | 0.5 | 0.63 | 0.82 | mA | 5VDC; VI=0V for π14xEx0 | 8 |
| Quiescent Supply Current, side 2 (5VDC, VI=5V) | IDD2 (Q) | 1.28 | 1.6 | 2.07 | mA | 5VDC; VI=5V for π14xEx1 | 8 |
| Quiescent Supply Current, side 1 (5VDC, VI=5V) | IDD1 (Q) | 0.75 | 0.94 | 1.22 | mA | 5VDC; VI=5V for π14xEx0 | 8 |
| Quiescent Supply Current, side 2 (5VDC, VI=0V) | IDD2 (Q) | 1.17 | 1.47 | 1.91 | mA | 5VDC; VI=0V for π14xEx1 | 8 |
| Quiescent Supply Current, side 1 (3.3VDC, VI=0V) | IDD1 (Q) | 0.48 | 0.6 | 0.78 | mA | 3.3VDC; VI=0V for π14xEx0 | 8 |
| Quiescent Supply Current, side 2 (3.3VDC, VI=3.3V) | IDD2 (Q) | 1.24 | 1.55 | 2.01 | mA | 3.3VDC; VI=3.3V for π14xEx1 | 8 |
| Quiescent Supply Current, side 1 (3.3VDC, VI=3.3V) | IDD1 (Q) | 0.61 | 0.77 | 1 | mA | 3.3VDC; VI=3.3V for π14xEx0 | 8 |
| Quiescent Supply Current, side 2 (3.3VDC, VI=0V) | IDD2 (Q) | 1.13 | 1.42 | 1.84 | mA | 3.3VDC; VI=0V for π14xEx1 | 8 |
| Rated Dielectric Insulation Voltage | 5000 | V rms | 1-minute duration | 9 | |||
| Minimum External Air Gap (Clearance) | L(CLR) | 8 | mm | Measured from input terminals to output terminals, shortest distance through air | 9 | ||
| Minimum External Tracking (Creepage) | L(CRP) | 8 | mm | Measured from input terminals to output terminals, shortest distance path along body | 9 | ||
| Minimum Internal Gap (Internal Clearance) | 21 | µm | Insulation distance through insulation | 9 | |||
| Tracking Resistance (Comparative Tracking Index) | CTI | 400 | V | DIN EN 60112 (VDE 0303-11):2010-05 | 9 | ||
| Common-Mode Transient Immunity | CMTI | 120 | kV/µs | 1 | |||
| Capacitance (Input to Output) | CIO | 1.5 | pF | @1MHz | 9 | ||
| Input Capacitance | CI | 3 | pF | @1MHz | 9 | ||
| IC Junction to Ambient Thermal Resistance | θJA | 45 | °C/W | Thermocouple located at center of package underside | 9 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN V VDE V 0884-11, each π140E3x/π141E3x/π142E3x is proof tested by applying an insulation test voltage ≥ 848 V peak for 1 sec (partial discharge detection limit = 5 pC); each π140 | 10 |
CAD (KiCad official)
- Symbol:
π141E61 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
141e61-etched.step/141e61-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);141e61.step/141e61.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 2Pai Semi datasheet (20 pp, sha256
5e3887ddbec8e982, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# π141E61
**2Pai Semi** · Digital Isolators · SOIC-16-300mil
π141E61 from 2Pai Semi, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, operating from 3 V to 5.5 V. |
| 2 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 3 | VIA | input | Logic input A; high-level input needs at least 0.7×VDDx1 and low-level input at most 0.3×VDDx1. |
| 4 | VIB | input | Logic input B; high-level input needs at least 0.7×VDDx1 and low-level input at most 0.3×VDDx1. |
| 5 | VIC | input | Logic input C; high-level input needs at least 0.7×VDDx1 and low-level input at most 0.3×VDDx1. |
| 6 | VOD | output | Logic output D on side 1; the datasheet limits output current to IOH −6 mA and IOL 6 mA. |
| 7 | NC/EN1 | input | Output enable 1 for π141E6X: side-1 outputs are enabled when EN1 is high or open and are high-impedance when EN1 is low (no connect on π141E3X). |
| 8 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 9 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 10 | NC/EN2 | input | Output enable 2 for π141E6X: side-2 outputs are enabled when EN2 is high or open and are high-impedance when EN2 is low (no connect on π141E3X). |
| 11 | VID | input | Logic input D; high-level input needs at least 0.7×VDDx2 and low-level input at most 0.3×VDDx2. |
| 12 | VOC | output | Logic output C on side 2; the datasheet limits output current to IOH −6 mA and IOL 6 mA. |
| 13 | VOB | output | Logic output B on side 2; the datasheet limits output current to IOH −6 mA and IOL 6 mA. |
| 14 | VOA | output | Logic output A on side 2; the datasheet limits output current to IOH −6 mA and IOL 6 mA. |
| 15 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 16 | VDD2 | power_in | Supply voltage for isolator side 2, operating from 3 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDDx | 3 | | 5.5 | V | | 4 |
| Low Level Input Signal Voltage | VIL | 0 | | | V | | 4 |
| High Level Output Current | IOH | -6 | | | mA | | 4 |
| Low Level Output Current | IOL | | | 6 | mA | | 4 |
| Data Rate | | 0 | | 200 | Mbps | | 4 |
| Junction Temperature | TJ | -40 | | 150 | °C | | 4 |
| Ambient Operating Temperature | TA | -40 | | 125 | °C | | 4 |
| Supply Voltages (VDD1-GND1, VDD2-GND2) | | -0.5 | | 7 | V | | 3 |
| Input Voltages (VIA, VIB) | | -0.5 | | | V | | 3 |
| Output Voltages (VOA, VOB) | | -0.5 | | | V | | 3 |
| Average Output Current per Pin, Side 1 | IO1 | -10 | | 10 | mA | | 3 |
| Average Output Current per Pin, Side 2 | IO2 | -10 | | 10 | mA | | 3 |
| Common-Mode Transients Immunity | | -200 | | 200 | kV/µs | | 3 |
| Storage Temperature Range | TST | -65 | | 150 | °C | | 3 |
| Ambient Operating Temperature Range | TA | -40 | | 125 | °C | | 3 |
| Minimum Pulse Width | PW | 5 | | | ns | Within pulse width distortion (PWD) limit | 5 |
| Maximum Data Rate | | | | 200 | Mbps | Within PWD limit | 5 |
| Propagation Delay Time, 5VDC supply | tpHL, tpLH | | 12 | 16 | ns | 5VDC supply | 5 |
| Propagation Delay Time, 3.3VDC supply | tpHL, tpLH | | 14 | 18.5 | ns | 3.3VDC supply | 5 |
| Pulse Width Distortion, 5VDC supply | PWD | | 0.3 | 3 | ns | The max different time between tpHL and tpLH @ 5VDC supply. And the value is / tpHL - tpLH / | 5 |
| Quiescent Supply Current, side 1 (5VDC, VI=0V) | IDD1 (Q) | 0.5 | 0.63 | 0.82 | mA | 5VDC; VI=0V for π14xEx0 | 8 |
| Quiescent Supply Current, side 2 (5VDC, VI=5V) | IDD2 (Q) | 1.28 | 1.6 | 2.07 | mA | 5VDC; VI=5V for π14xEx1 | 8 |
| Quiescent Supply Current, side 1 (5VDC, VI=5V) | IDD1 (Q) | 0.75 | 0.94 | 1.22 | mA | 5VDC; VI=5V for π14xEx0 | 8 |
| Quiescent Supply Current, side 2 (5VDC, VI=0V) | IDD2 (Q) | 1.17 | 1.47 | 1.91 | mA | 5VDC; VI=0V for π14xEx1 | 8 |
| Quiescent Supply Current, side 1 (3.3VDC, VI=0V) | IDD1 (Q) | 0.48 | 0.6 | 0.78 | mA | 3.3VDC; VI=0V for π14xEx0 | 8 |
| Quiescent Supply Current, side 2 (3.3VDC, VI=3.3V) | IDD2 (Q) | 1.24 | 1.55 | 2.01 | mA | 3.3VDC; VI=3.3V for π14xEx1 | 8 |
| Quiescent Supply Current, side 1 (3.3VDC, VI=3.3V) | IDD1 (Q) | 0.61 | 0.77 | 1 | mA | 3.3VDC; VI=3.3V for π14xEx0 | 8 |
| Quiescent Supply Current, side 2 (3.3VDC, VI=0V) | IDD2 (Q) | 1.13 | 1.42 | 1.84 | mA | 3.3VDC; VI=0V for π14xEx1 | 8 |
| Rated Dielectric Insulation Voltage | | | | 5000 | V rms | 1-minute duration | 9 |
| Minimum External Air Gap (Clearance) | L(CLR) | 8 | | | mm | Measured from input terminals to output terminals, shortest distance through air | 9 |
| Minimum External Tracking (Creepage) | L(CRP) | 8 | | | mm | Measured from input terminals to output terminals, shortest distance path along body | 9 |
| Minimum Internal Gap (Internal Clearance) | | 21 | | | µm | Insulation distance through insulation | 9 |
| Tracking Resistance (Comparative Tracking Index) | CTI | 400 | | | V | DIN EN 60112 (VDE 0303-11):2010-05 | 9 |
| Common-Mode Transient Immunity | CMTI | | 120 | | kV/µs | | 1 |
| Capacitance (Input to Output) | CIO | | 1.5 | | pF | @1MHz | 9 |
| Input Capacitance | CI | | 3 | | pF | @1MHz | 9 |
| IC Junction to Ambient Thermal Resistance | θJA | | 45 | | °C/W | Thermocouple located at center of package underside | 9 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | | In accordance with DIN V VDE V 0884-11, each π140E3x/π141E3x/π142E3x is proof tested by applying an insulation test voltage ≥ 848 V peak for 1 sec (partial discharge detection limit = 5 pC); each π140 | 10 |
## CAD (KiCad official)
- Symbol: `π141E61`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files: `141e61-etched.step` / `141e61-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `141e61.step` / `141e61.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [2Pai Semi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590904577325809664) (20 pp, sha256 `5e3887ddbec8e982`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/141e61-datasheet.pdf)