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Contents

README

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π140E31

2Pai Semi · Digital Isolators · SOIC-16

π140E31 from 2Pai Semi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, recommended 3 V to 5.5 V with a 0.1 µF to 10 µF bypass capacitor to GND1.
2 GND1 power_in Ground 1, the ground reference for isolator side 1.
3 VIA input Logic input A on side 1.
4 VIB input Logic input B on side 1.
5 VIC input Logic input C on side 1.
6 VID input Logic input D on side 1.
7 NC unconnected No connect.
8 GND1 power_in Ground 1, the ground reference for isolator side 1.
9 GND2 power_in Ground 2, the ground reference for isolator side 2.
10 NC unconnected No connect for the π140E3X (this pin is the EN2 output enable only on the π140E6X).
11 VOD output Logic output D on side 2, rated for 6 mA high and low level output current.
12 VOC output Logic output C on side 2, rated for 6 mA high and low level output current.
13 VOB output Logic output B on side 2, rated for 6 mA high and low level output current.
14 VOA output Logic output A on side 2, rated for 6 mA high and low level output current.
15 GND2 power_in Ground 2, the ground reference for isolator side 2.
16 VDD2 power_in Supply voltage for isolator side 2, recommended 3 V to 5.5 V with a 0.1 µF to 10 µF bypass capacitor to GND2.

Key specifications

Parameter Value
Manufacturer 2Pai Semi
Package SOIC-16
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDDx 3 5.5 V 3
High Level Input Signal Voltage VIH 0.7 V min is 0.7*VDDx; max is VDDx 3
Low Level Input Signal Voltage VIL 0 0.3 V max is 0.3*VDDx 4
High Level Output Current IOH -6 mA 4
Low Level Output Current IOL 6 mA 4
Data Rate 0 200 Mbps 4
Junction Temperature TJ -40 150 °C 4
Ambient Operating Temperature TA -40 125 °C 4
Supply Voltages VDD1-GND1, VDD2-GND2 -0.5 7 V TA = 25°C 3
Input Voltages VIA, VIB -0.5 0.5 V max is VDDx + 0.5 V 3
Output Voltages VOA, VOB -0.5 0.5 V max is VDDx + 0.5 V 3
Average Output Current per Pin, Side 1 IO1 -10 10 mA 3
Average Output Current per Pin, Side 2 IO2 -10 10 mA 3
Common-Mode Transients Immunity -200 200 kV/µs 3
Storage Temperature TST -65 150 °C 3
Ambient Operating Temperature TA -40 125 °C 3
Propagation Delay Time tpHL, tpLH 5.5 8 12.5 ns 5VDC supply 5
Propagation Delay Time tpHL, tpLH 6.5 9 13.5 ns 3.3VDC supply 5
Minimum Pulse Width PW 5 ns Within pulse width distortion (PWD) limit 4
Maximum Data Rate 200 Mbps Within PWD limit 5
Pulse Width Distortion PWD 0.3 3 ns 5VDC supply; /tpHL - tpLH/ 5
Pulse Width Distortion PWD 0.4 3 ns 3.3VDC supply; /tpHL - tpLH/ 5
Part to Part Propagation Delay Skew tPSK 2 ns 5VDC supply 5
Channel to Channel Propagation Delay Skew tCSK 0 1.8 ns 5VDC supply 5
Channel to Channel Propagation Delay Skew tCSK 0 2 ns 3.3VDC supply 5
IC Junction to Ambient Thermal Resistance θJA 100 °C/W Thermocouple located at center of package underside 9
Output Signal Rise/Fall Time tr/tf 1.5 ns See Figure 10. 5
Common-Mode Transient Immunity CMTI 75 kV/µs VIN = VDDx or 0V, VCM = 1000 V 5
ESD (HBM) ESD -8 8 kV 5
Dynamic Input Supply Current per Channel IDDI (D) 9 µA/Mbps Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC Supply 5
Dynamic Output Supply Current per Channel IDDO (D) 38 µA/Mbps Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC Supply 5
Dynamic Input Supply Current per Channel IDDI (D) 5 µA/Mbps Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC Supply 5
Dynamic Output Supply Current per Channel IDDO (D) 23 µA/Mbps Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC Supply 5
Jitter (peak-to-peak) 120 ps p-p See the Jitter Measurement section 5
Jitter (rms) 20 ps rms See the Jitter Measurement section 5
Rated Dielectric Insulation Voltage 3000 V rms 1-minute duration 9
Input Capacitance CI 3 pF @1MHz 9
Capacitance (Input to Output) CIO 1.5 pF @1MHz 9

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN V VDE V 0884-11, each π140E3x/π141E3x/π142E3x is proof tested by applying an insulation test voltage ≥ 848 V peak for 1 sec (partial discharge detection limit = 5 pC); each π140 10

CAD (KiCad official)

  • Symbol: π140E31
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 140e31-etched.step / 140e31-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 140e31.step / 140e31.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 2Pai Semi datasheet (20 pp, sha256 5e3887ddbec8e982, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF