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π122U31
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2Pai Semi Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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π122U31
2Pai Semi · Digital Isolators · SOIC-8
π122U31 from 2Pai Semi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, which the datasheet specifies as 3 V to 5.5 V (VDDx). |
| 2 | VOA | output | Logic output A, with the output high level bounded by VDDx and the default output state set by the part's fail-safe option (High for π122U31). |
| 3 | VIB | input | Logic input B, with high-level input thresholds of 0.7VDDx to VDDx and low-level input thresholds of 0 to 0.3VDDx. |
| 4 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 5 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 6 | VOB | output | Logic output B, with the output high level bounded by VDDx and the default output state set by the part's fail-safe option. |
| 7 | VIA | input | Logic input A, with high-level input thresholds of 0.7VDDx to VDDx and low-level input thresholds of 0 to 0.3VDDx. |
| 8 | VDD2 | power_in | Supply voltage for isolator side 2, which the datasheet specifies as 3 V to 5.5 V (VDDx). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltages (VDD1-GND1, VDD2-GND2) | -0.5 | 7 | V | 4 | |||
| Average Output Current per Pin, Side 1 | IO1 | -10 | 10 | mA | 4 | ||
| Average Output Current per Pin, Side 2 | IO2 | -10 | 10 | mA | 4 | ||
| Common-Mode Transients Immunity | -150 | 150 | kV/µs | 4 | |||
| Storage Temperature Range | TST | -65 | 150 | °C | 4 | ||
| Ambient Operating Temperature Range | TA | -40 | 125 | °C | 4 | ||
| Supply Voltage | VDDx | 3 | 5.5 | V | 4 | ||
| Low Level Input Signal Voltage | VIL | 0 | V | 4 | |||
| High Level Output Current | IOH | -6 | mA | 4 | |||
| Low Level Output Current | IOL | 6 | mA | 4 | |||
| Maximum Data Rate | 0 | 150 | Kbps | 4 | |||
| Junction Temperature | TJ | -40 | 150 | °C | 4 | ||
| Ambient Operating Temperature | TA | -40 | 125 | °C | 4 | ||
| Minimum Pulse Width | PW | 6.5 | us | Within pulse width distortion (PWD) limit | 5 | ||
| Maximum Data Rate | 150 | Kbps | Within PWD limit | 5 | |||
| Propagation Delay Time | tpHL, tpLH | 3 | 4.5 | us | 50% input to 50% output, 50% @ 5VDC supply | 5 | |
| Propagation Delay Time | tpHL, tpLH | 3.2 | 4.8 | us | 50% input to 50% output, @ 3.3VDC supply | 5 | |
| Pulse Width Distortion | PWD | 0 | 0.02 | 0.2 | us | /tpHL - tpLH/, @ 5VDC supply | 5 |
| Part to Part Propagation Delay Skew | tPSK | 0.3 | us | Max difference between any two devices, @ 5VDC supply | 5 | ||
| Channel to Channel Propagation Delay Skew | tCSK | 0 | 0.2 | us | @ 5VDC supply | 5 | |
| Output Signal Rise/Fall Time | tr/tf | 1.5 | ns | 10% to 90% signal, terminated 50 Ω | 5 | ||
| Common-Mode Transient Immunity | CMTI | 100 | 150 | kV/µs | VIN = VDDx2 or 0V, VCM = 1000 V | 5 | |
| ESD (HBM - Human Body Model) | ESD | -8 | 8 | kV | All pins | 5 | |
| Low Level Output Voltage | VOL | 0 | 0.1 | V | 20 µA output current | 5 | |
| Low Level Output Voltage | VOL | 0.1 | 0.2 | V | 2 mA output current | 6 | |
| Input Current per Signal Channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ Signal voltage ≤ VDDX1 | 6 |
| VDDx1 Undervoltage Rising Threshold | VDDxUV+ | 2.45 | 2.65 | 2.9 | V | 6 | |
| VDDx1 Undervoltage Falling Threshold | VDDxUV− | 2.3 | 2.5 | 2.75 | V | 6 | |
| VDDx1 Hysteresis | VDDxUVH | 0.15 | V | 6 | |||
| Quiescent Supply Current, side 1 | IDD1 (Q) | 431 | 539 | 701 | µA | @ 5VDC supply, 0V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 2 | IDD2 (Q) | 431 | 539 | 701 | µA | @ 5VDC supply, 0V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 1 | IDD1 (Q) | 414 | 518 | 673 | µA | @ 5VDC supply, 5V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 2 | IDD2 (Q) | 414 | 518 | 673 | µA | @ 5VDC supply, 5V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 1 | IDD1 (Q) | 405 | 506 | 658 | µA | @ 3.3VDC supply, 0V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 2 | IDD2 (Q) | 405 | 506 | 658 | µA | @ 3.3VDC supply, 0V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 1 | IDD1 (Q) | 410 | 512 | 666 | µA | @ 3.3VDC supply, 3.3V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 2 | IDD2 (Q) | 410 | 512 | 666 | µA | @ 3.3VDC supply, 3.3V input signal, CL = 0 pF | 6 |
| Rated Dielectric Insulation Voltage (U3x) | 3000 | V rms | 1-minute duration | 7 | |||
| Minimum External Air Gap (Clearance) (U3x) | L (CLR) | 4 | mm | Input terminals to output terminals, shortest distance through air | 7 | ||
| Minimum External Tracking (Creepage) (U3x) | L (CRP) | 4 | mm | Input terminals to output terminals, shortest distance along body | 7 | ||
| Minimum Internal Gap (Internal Clearance) (U3x) | 11 | µm | Insulation distance through insulation | 7 | |||
| Tracking Resistance (Comparative Tracking Index) (U3x) | CTI | 400 | V | DIN IEC 112/VDE 0303 Part 1; printed as >400 | 7 | ||
| IC Junction to Ambient Thermal Resistance (U3x) | θJA | 100 | °C/W | Thermocouple located at center of package underside | 7 | ||
| Input Capacitance | CI | 3 | pF | @1MHz | 7 | ||
| Capacitance (Input to Output) (U3x) | CI-O | 0.6 | pF | @1MHz | 7 | ||
| Maximum Working Insulation Voltage (U3x) | VIORM | 707 | V peak | DIN VDE 0884-10 | 8 | ||
| Highest Allowable Overvoltage (U3x) | VIOTM | 4200 | V peak | 8 | |||
| Surge Isolation Voltage Basic (U3x) | VIOSM | 4615 | V peak | Basic insulation, 1.2 µs rise time, 50 µs, 50% fall time | 9 | ||
| Maximum Junction Temperature (safety limiting) | TS | 150 | °C | Maximum value allowed in the event of a failure | 9 | ||
| Total Power Dissipation at 25°C (safety limiting) | PS | 1.56 | W | At 25°C | 9 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN V VDE V 0884-10, each π120U3x/π121U3x/π122U3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial discharge detection limit = 5 pC); each π12 | 8 |
CAD (KiCad official)
- Symbol:
π122U31 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
122u31-etched.step/122u31-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);122u31.step/122u31.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 2Pai Semi datasheet (15 pp, sha256
9446a9f1f049ff4b, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# π122U31
**2Pai Semi** · Digital Isolators · SOIC-8
π122U31 from 2Pai Semi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, which the datasheet specifies as 3 V to 5.5 V (VDDx). |
| 2 | VOA | output | Logic output A, with the output high level bounded by VDDx and the default output state set by the part's fail-safe option (High for π122U31). |
| 3 | VIB | input | Logic input B, with high-level input thresholds of 0.7*VDDx to VDDx and low-level input thresholds of 0 to 0.3*VDDx. |
| 4 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 5 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 6 | VOB | output | Logic output B, with the output high level bounded by VDDx and the default output state set by the part's fail-safe option. |
| 7 | VIA | input | Logic input A, with high-level input thresholds of 0.7*VDDx to VDDx and low-level input thresholds of 0 to 0.3*VDDx. |
| 8 | VDD2 | power_in | Supply voltage for isolator side 2, which the datasheet specifies as 3 V to 5.5 V (VDDx). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltages (VDD1-GND1, VDD2-GND2) | | -0.5 | | 7 | V | | 4 |
| Average Output Current per Pin, Side 1 | IO1 | -10 | | 10 | mA | | 4 |
| Average Output Current per Pin, Side 2 | IO2 | -10 | | 10 | mA | | 4 |
| Common-Mode Transients Immunity | | -150 | | 150 | kV/µs | | 4 |
| Storage Temperature Range | TST | -65 | | 150 | °C | | 4 |
| Ambient Operating Temperature Range | TA | -40 | | 125 | °C | | 4 |
| Supply Voltage | VDDx | 3 | | 5.5 | V | | 4 |
| Low Level Input Signal Voltage | VIL | 0 | | | V | | 4 |
| High Level Output Current | IOH | -6 | | | mA | | 4 |
| Low Level Output Current | IOL | | | 6 | mA | | 4 |
| Maximum Data Rate | | 0 | | 150 | Kbps | | 4 |
| Junction Temperature | TJ | -40 | | 150 | °C | | 4 |
| Ambient Operating Temperature | TA | -40 | | 125 | °C | | 4 |
| Minimum Pulse Width | PW | 6.5 | | | us | Within pulse width distortion (PWD) limit | 5 |
| Maximum Data Rate | | | | 150 | Kbps | Within PWD limit | 5 |
| Propagation Delay Time | tpHL, tpLH | 3 | | 4.5 | us | 50% input to 50% output, 50% @ 5VDC supply | 5 |
| Propagation Delay Time | tpHL, tpLH | 3.2 | | 4.8 | us | 50% input to 50% output, @ 3.3VDC supply | 5 |
| Pulse Width Distortion | PWD | 0 | 0.02 | 0.2 | us | /tpHL - tpLH/, @ 5VDC supply | 5 |
| Part to Part Propagation Delay Skew | tPSK | | | 0.3 | us | Max difference between any two devices, @ 5VDC supply | 5 |
| Channel to Channel Propagation Delay Skew | tCSK | 0 | | 0.2 | us | @ 5VDC supply | 5 |
| Output Signal Rise/Fall Time | tr/tf | | | 1.5 | ns | 10% to 90% signal, terminated 50 Ω | 5 |
| Common-Mode Transient Immunity | CMTI | 100 | 150 | | kV/µs | VIN = VDDx2 or 0V, VCM = 1000 V | 5 |
| ESD (HBM - Human Body Model) | ESD | -8 | | 8 | kV | All pins | 5 |
| Low Level Output Voltage | VOL | 0 | | 0.1 | V | 20 µA output current | 5 |
| Low Level Output Voltage | VOL | 0.1 | | 0.2 | V | 2 mA output current | 6 |
| Input Current per Signal Channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ Signal voltage ≤ VDDX1 | 6 |
| VDDx1 Undervoltage Rising Threshold | VDDxUV+ | 2.45 | 2.65 | 2.9 | V | | 6 |
| VDDx1 Undervoltage Falling Threshold | VDDxUV− | 2.3 | 2.5 | 2.75 | V | | 6 |
| VDDx1 Hysteresis | VDDxUVH | | 0.15 | | V | | 6 |
| Quiescent Supply Current, side 1 | IDD1 (Q) | 431 | 539 | 701 | µA | @ 5VDC supply, 0V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 2 | IDD2 (Q) | 431 | 539 | 701 | µA | @ 5VDC supply, 0V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 1 | IDD1 (Q) | 414 | 518 | 673 | µA | @ 5VDC supply, 5V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 2 | IDD2 (Q) | 414 | 518 | 673 | µA | @ 5VDC supply, 5V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 1 | IDD1 (Q) | 405 | 506 | 658 | µA | @ 3.3VDC supply, 0V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 2 | IDD2 (Q) | 405 | 506 | 658 | µA | @ 3.3VDC supply, 0V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 1 | IDD1 (Q) | 410 | 512 | 666 | µA | @ 3.3VDC supply, 3.3V input signal, CL = 0 pF | 6 |
| Quiescent Supply Current, side 2 | IDD2 (Q) | 410 | 512 | 666 | µA | @ 3.3VDC supply, 3.3V input signal, CL = 0 pF | 6 |
| Rated Dielectric Insulation Voltage (U3x) | | | | 3000 | V rms | 1-minute duration | 7 |
| Minimum External Air Gap (Clearance) (U3x) | L (CLR) | 4 | | | mm | Input terminals to output terminals, shortest distance through air | 7 |
| Minimum External Tracking (Creepage) (U3x) | L (CRP) | 4 | | | mm | Input terminals to output terminals, shortest distance along body | 7 |
| Minimum Internal Gap (Internal Clearance) (U3x) | | 11 | | | µm | Insulation distance through insulation | 7 |
| Tracking Resistance (Comparative Tracking Index) (U3x) | CTI | 400 | | | V | DIN IEC 112/VDE 0303 Part 1; printed as >400 | 7 |
| IC Junction to Ambient Thermal Resistance (U3x) | θJA | | 100 | | °C/W | Thermocouple located at center of package underside | 7 |
| Input Capacitance | CI | | 3 | | pF | @1MHz | 7 |
| Capacitance (Input to Output) (U3x) | CI-O | | 0.6 | | pF | @1MHz | 7 |
| Maximum Working Insulation Voltage (U3x) | VIORM | | | 707 | V peak | DIN VDE 0884-10 | 8 |
| Highest Allowable Overvoltage (U3x) | VIOTM | | | 4200 | V peak | | 8 |
| Surge Isolation Voltage Basic (U3x) | VIOSM | | | 4615 | V peak | Basic insulation, 1.2 µs rise time, 50 µs, 50% fall time | 9 |
| Maximum Junction Temperature (safety limiting) | TS | | | 150 | °C | Maximum value allowed in the event of a failure | 9 |
| Total Power Dissipation at 25°C (safety limiting) | PS | | | 1.56 | W | At 25°C | 9 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | | In accordance with DIN V VDE V 0884-10, each π120U3x/π121U3x/π122U3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial discharge detection limit = 5 pC); each π12 | 8 |
## CAD (KiCad official)
- Symbol: `π122U31`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `122u31-etched.step` / `122u31-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `122u31.step` / `122u31.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [2Pai Semi datasheet](docs/122u31-datasheet.pdf) (15 pp, sha256 `9446a9f1f049ff4b`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/122u31-datasheet.pdf)