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π122E30Q

Public Made by Adom

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2Pai Semi Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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π122E30Q

2Pai Semi · Digital Isolators · SOIC-8

π122E30Q from 2Pai Semi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, specified at 3 V to 5.5 V in the recommended operating conditions, with side-1 undervoltage lockout rising at 2.45 to 2.95 V.
2 VOA output Logic output A on the side-2 supply, with VOH of VDDx − 0.1 V at −20 µA and VOL of 0.1 V max at 2 mA, and a rated output current of −6 mA to 6 mA.
3 VIB input Logic input B on the side-1 supply, with VIH of 0.7×VDDx1 min and VIL of 0.3×VDDx1 max, and fail-safe default output Low for this ordering option.
4 GND1 power_in Ground reference for isolator side 1 (VDD1 side).
5 GND2 power_in Ground reference for isolator side 2 (VDD2 side).
6 VOB output Logic output B on the side-2 supply, with VOH of VDDx − 0.1 V at −20 µA and VOL of 0.1 V max at 2 mA, and a rated output current of −6 mA to 6 mA.
7 VIA input Logic input A on the side-1 supply, with VIH of 0.7×VDDx1 min and VIL of 0.3×VDDx1 max, and fail-safe default output Low for this ordering option.
8 VDD2 power_in Supply voltage for isolator side 2, specified at 3 V to 5.5 V in the recommended operating conditions, with side-2 undervoltage lockout rising at 2.45 to 2.95 V.

Key specifications

Parameter Value
Manufacturer 2Pai Semi
Package SOIC-8
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltages (VDD1-GND1, VDD2-GND2) -0.5 7 V 3
Input Voltages (VIA, VIB) -0.5 V 3
Output Voltages (VOA, VOB) -0.5 V 3
Average Output Current per Pin, Side 1 IO1 -10 10 mA 3
Average Output Current per Pin, Side 2 IO2 -10 10 mA 3
Common-Mode Transients Immunity -200 200 kV/µs 3
Storage Temperature Range TST -65 150 °C 3
Ambient Operating Temperature Range TA -40 125 °C 3
Supply Voltage VDDx 3 5.5 V 4
Low Level Input Signal Voltage VIL 0 V 4
High Level Output Current IOH -6 mA 4
Low Level Output Current IOL 6 mA 4
Data Rate 0 200 Mbps 4
Junction Temperature TJ -40 150 °C 4
Ambient Operating Temperature TA -40 125 °C 4
Minimum Pulse Width PW 5 ns Within pulse width distortion (PWD) limit 4
Maximum Data Rate 200 Mbps Within PWD limit 4
Propagation Delay Time tpHL, tpLH 5.5 8 12.5 ns @ 5VDC supply 4
Propagation Delay Time tpHL, tpLH 6.5 9 13.5 ns @ 3.3VDC supply 4
Pulse Width Distortion PWD 0.3 3 ns @ 5VDC supply; value is /tpHL - tpLH/ 4
Pulse Width Distortion PWD 0.4 3 ns @ 3.3VDC supply; value is /tpHL - tpLH/ 4
Part to Part Propagation Delay Skew tPSK 2 ns @ 5VDC supply 5
Channel to Channel Propagation Delay Skew tCSK 0 1.8 ns @ 5VDC supply 5
Channel to Channel Propagation Delay Skew tCSK 0 2 ns @ 3.3VDC supply 5
Output Signal Rise/Fall Time tr/tf 1.5 ns See Figure 13 5
Electrical Characteristics: Dynamic Input Supply Current per Channel IDDI (D) 9 µA/Mbps Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC supply 5
Dynamic Output Supply Current per Channel IDDO (D) 38 µA/Mbps Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC supply 5
Dynamic Input Supply Current per Channel IDDI (D) 5 µA/Mbps Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC supply 5
Dynamic Output Supply Current per Channel IDDO (D) 23 µA/Mbps Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC supply 5
Common-Mode Transient Immunity CMTI 75 kV/µs VIN = VDDx2 or 0V, VCM = 1000 V 5
Jitter (peak-to-peak) 120 ps p-p See the Jitter Measurement section 5
Jitter (rms) 20 ps rms See the Jitter Measurement section 5
ESD Human Body Model ESD -8 8 kV HBM (Human body model) 5
Low Level Output Voltage VOL 0 0.1 V 20 µA output current 6
Low Level Output Voltage VOL 0.1 0.2 V 2 mA output current 6
Input Current per Signal Channel IIN -10 0.5 10 µA 0 V ≤ Signal voltage ≤ VDDX1 6
VDDx1 Undervoltage Rising Threshold VDDxUV+ 2.45 2.75 2.95 V 6
VDDx1 Undervoltage Falling Threshold VDDxUV− 2.3 2.6 2.75 V 6
VDDx1 Hysteresis VDDxUVH 0.15 V 6
Quiescent Supply Current, side 1 IDD1 (Q) 0.42 0.52 0.68 mA 5VDC; VI=0V for π12xEx0 6
Quiescent Supply Current, side 2 IDD2 (Q) 0.42 0.52 0.68 mA 5VDC; VI=5V for π12xEx1 6
Quiescent Supply Current, side 1 IDD1 (Q) 0.44 0.55 0.71 mA 5VDC; VI=5V for π12xEx0 6
Quiescent Supply Current, side 2 IDD2 (Q) 0.44 0.55 0.71 mA 5VDC; VI=0V for π12xEx1 6
Quiescent Supply Current, side 1 IDD1 (Q) 0.41 0.52 0.67 mA 3.3VDC; VI=0V for π12xEx0 7
Quiescent Supply Current, side 2 IDD2 (Q) 0.41 0.52 0.67 mA 3.3VDC; VI=3.3V for π12xEx1 7
Quiescent Supply Current, side 1 IDD1 (Q) 0.41 0.51 0.66 mA 3.3VDC; VI=3.3V for π12xEx0 7
Quiescent Supply Current, side 2 IDD2 (Q) 0.41 0.51 0.66 mA 3.3VDC; VI=0V for π12xEx1 7
Minimum External Air Gap (Clearance) L (CLR) 4 mm Measured from input terminals to output terminals, shortest distance through air 8
Minimum External Tracking (Creepage) L (CRP) 4 mm Measured from input terminals to output terminals, shortest distance path along body 8
Minimum Internal Gap (Internal Clearance) 11 µm Insulation distance through insulation 8
Tracking Resistance (Comparative Tracking Index) CTI 400 V DIN EN 60112 (VDE 0303-11):2010-05; printed as >400 8
Maximum Repetitive Peak Isolation Voltage VIORM 565 V peak DIN VDE V 0884-11 (π12xE3x) 9
Highest Allowable Overvoltage VIOTM 4200 V peak DIN VDE V 0884-11 (π12xE3x) 9
Surge Isolation Voltage Basic VIOSM 3615 V peak Basic insulation, 1.2/50 µs combination wave, VTEST = 1.3 × VIOSM (qualification) 9
Maximum Safety Temperature TS 150 °C Safety limiting value (π12xE3x) 9
Maximum Power Dissipation at 25°C PS 1.25 W Safety limiting value at 25°C (π12xE3x) 9
Rated Dielectric Insulation Voltage 3000 V rms 1-minute duration (π12xE3x) 8
Thermal Resistance, Junction to Ambient (NB SOIC-8) θJA 100 °C/W Thermocouple located at center of package underside (π12xE3x) 9

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN V VDE V 0884-11, each π120E3x/π121E3x/π122E3x is proof tested by applying an insulation test voltage ≥ 848 V peak for 1 sec (partial discharge detection limit = 5 pC); each π120 9

CAD (KiCad official)

  • Symbol: π122E30Q
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: 122e30q-etched.step / 122e30q-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 122e30q.step / 122e30q.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 2Pai Semi datasheet (18 pp, sha256 46f1f75769a4de29, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF