component
π121M30
Public Made by Adomby adom
2Pai Semi Digital Isolators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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π121M30
2Pai Semi · Digital Isolators · SOP-8
π121M30 from 2Pai Semi, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Primary-side isolator supply, which operates from 3.0 V to 5.5 V and should be bypassed to GND1 with a low-ESR ceramic capacitor of 0.1 µF to 10 µF placed as close to the device as possible. |
| 2 | VIA | input | Channel A input on the primary side; logic high requires at least 0.7×VDD1 and logic low is at most 0.3×VDD1, with the absolute maximum input range of −0.5 V to VDD1 + 0.5 V. |
| 3 | VOB | output | Channel B output on the secondary side, rated for IOH of −6 mA and IOL of 6 mA under recommended conditions, with absolute maximum output voltage of −0.5 V to VDD2 + 0.5 V; the π121M30 default output level is Low when the input side is unpowered. |
| 4 | GND1 | power_in | Primary-side ground reference for VDD1 and the channel A and B inputs. |
| 5 | GND2 | power_in | Secondary-side ground reference for VDD2 and the channel A and B outputs, rated for 3000 Vrms isolation for 1 minute with GND1. |
| 6 | VIB | input | Channel B input on the primary side; logic high requires at least 0.7×VDD1 and logic low is at most 0.3×VDD1, with the absolute maximum input range of −0.5 V to VDD1 + 0.5 V. |
| 7 | VOA | output | Channel A output on the secondary side, rated for IOH of −6 mA and IOL of 6 mA under recommended conditions, with absolute maximum output voltage of −0.5 V to VDD2 + 0.5 V. |
| 8 | VDD2 | power_in | Secondary-side isolator supply, which operates from 3.0 V to 5.5 V and should be bypassed to GND2 with a low-ESR ceramic capacitor of 0.1 µF to 10 µF. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOP-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDDx | 3 | 5.5 | V | 4 | ||
| Supply voltage (absolute maximum) | VDD1-GND1, VDD2-GND2 | -0.5 | 7 | V | 3 | ||
| Input signal voltage | VIA, VIB | -0.5 | V | upper limit printed as VDDx + 0.5 V | 3 | ||
| Output voltage | VOA, VOB | -0.5 | V | upper limit printed as VDDx + 0.5 V | 3 | ||
| Primary per-channel average output current | IO1 | -10 | 10 | mA | 3 | ||
| Secondary per-channel average output current | IO2 | -10 | 10 | mA | 3 | ||
| Common-mode transient immunity | CMTI | -200 | 200 | kV/µs | 3 | ||
| Storage temperature range | TST | -65 | 150 | ℃ | 3 | ||
| Operating ambient temperature range (absolute maximum) | TA | -40 | 125 | ℃ | 3 | ||
| Input signal low level | VIL | 0 | V | upper limit printed as 0.3*VDDx1 V | 4 | ||
| High-level output current | IOH | -6 | mA | output high | 4 | ||
| Low-level output current | IOL | 6 | mA | output low | 4 | ||
| Communication rate | 0 | 10 | Mbps | 4 | |||
| Junction temperature | TJ | -40 | 150 | ℃ | 4 | ||
| Ambient temperature | TA | -40 | 125 | ℃ | 4 | ||
| Minimum pulse width | PW | 100 | ns | within pulse width distortion (PWD) limit | 4 | ||
| Maximum data rate | 10 | Mbps | within pulse width distortion (PWD) limit | 4 | |||
| Propagation delay tpHL, tpLH (5VDC supply) | tpHL, tpLH | 5.5 | 8 | 12.5 | ns | 5VDC supply | 4 |
| Propagation delay tpHL, tpLH (3.3VDC supply) | tpHL, tpLH | 6.5 | 9 | 13.5 | ns | 3.3VDC supply | 4 |
| Pulse width distortion (5VDC supply) | PWD | 0.3 | 3 | ns | 5VDC supply; max difference between tpHL and tpLH | 4 | |
| Pulse width distortion (3.3VDC supply) | PWD | 0.4 | 3 | ns | 3.3VDC supply; max difference between tpHL and tpLH | 4 | |
| Low-level output voltage | VOL | 0 | 0.1 | V | 20 µA output current | 6 | |
| Low-level output voltage | VOL | 0.1 | 0.2 | V | 2 mA output current | 6 | |
| Input current per channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ signal voltage ≤ VDDx1 | 6 |
| VDDx1 undervoltage threshold (rising) | VDDxUV+ | 2.45 | 2.75 | 2.95 | V | 6 | |
| VDDx1 undervoltage threshold (falling) | VDDxUV- | 2.3 | 2.6 | 2.75 | V | 6 | |
| Quiescent supply current IDD1 (5VDC, input low) | IDD1 (Q) | 0.42 | 0.52 | 0.68 | mA | 5VDC; π12xMx0 input low 0V | 6 |
| Quiescent supply current IDD2 (5VDC, x1 input high) | IDD2 (Q) | 0.42 | 0.52 | 0.68 | mA | 5VDC; π12xMx1 input high 5V | 6 |
| Quiescent supply current IDD1 (5VDC, input high) | IDD1 (Q) | 0.44 | 0.55 | 0.71 | mA | 5VDC; π12xMx0 input high 5V | 6 |
| Quiescent supply current IDD2 (5VDC, x1 input low) | IDD2 (Q) | 0.44 | 0.55 | 0.71 | mA | 5VDC; π12xMx1 input low 0V | 6 |
| Quiescent supply current IDD1 (3.3VDC, input low) | IDD1 (Q) | 0.41 | 0.52 | 0.67 | mA | 3.3VDC; π12xMx0 input low 0V | 6 |
| Quiescent supply current IDD2 (3.3VDC, x1 input high) | IDD2 (Q) | 0.41 | 0.52 | 0.67 | mA | 3.3VDC; π12xMx1 input high 3.3V | 6 |
| Quiescent supply current IDD1 (3.3VDC, input high) | IDD1 (Q) | 0.41 | 0.51 | 0.66 | mA | 3.3VDC; π12xMx0 input high 3.3V | 7 |
| Quiescent supply current IDD2 (3.3VDC, x1 input low) | IDD2 (Q) | 0.41 | 0.51 | 0.66 | mA | 3.3VDC; π12xMx1 input low 0V | 7 |
| Total supply current IDD1 at 150 Kbps (5VDC) | IDD1 | 0.54 | 0.81 | mA | CL=0pF; 150 Kbps; 5VDC | 7 | |
| Total supply current IDD1 at 1 Mbps (5VDC) | IDD1 | 0.58 | 0.86 | mA | CL=0pF; 1 Mbps; 5VDC | 7 | |
| Total supply current IDD1 at 10 Mbps (5VDC) | IDD1 | 0.97 | 1.46 | mA | CL=0pF; 10 Mbps; 5VDC | 7 | |
| Total supply current IDD2 at 150 Kbps (5VDC) | IDD2 | 0.54 | 0.81 | mA | CL=0pF; 150 Kbps; 5VDC | 7 | |
| Total supply current IDD2 at 1 Mbps (5VDC) | IDD2 | 0.58 | 0.86 | mA | CL=0pF; 1 Mbps; 5VDC | 7 | |
| Total supply current IDD2 at 10 Mbps (5VDC) | IDD2 | 0.97 | 1.46 | mA | CL=0pF; 10 Mbps; 5VDC | 7 | |
| Total supply current IDD1 at 150 Kbps (3.3VDC) | IDD1 | 0.52 | 0.78 | mA | CL=0pF; 150 Kbps; 3.3VDC | 7 | |
| Total supply current IDD1 at 1 Mbps (3.3VDC) | IDD1 | 0.54 | 0.81 | mA | CL=0pF; 1 Mbps; 3.3VDC | 7 | |
| Total supply current IDD1 at 10 Mbps (3.3VDC) | IDD1 | 0.77 | 1.16 | mA | CL=0pF; 10 Mbps; 3.3VDC | 7 | |
| Total supply current IDD2 at 150 Kbps (3.3VDC) | IDD2 | 0.52 | 0.78 | mA | CL=0pF; 150 Kbps; 3.3VDC | 7 | |
| Total supply current IDD2 at 1 Mbps (3.3VDC) | IDD2 | 0.54 | 0.81 | mA | CL=0pF; 1 Mbps; 3.3VDC | 7 | |
| Total supply current IDD2 at 10 Mbps (3.3VDC) | IDD2 | 0.77 | 1.16 | mA | CL=0pF; 10 Mbps; 3.3VDC | 7 | |
| Rated isolation voltage | 3000 | Vrms | 1 minute; π12xM3x | 8 | |||
| Maximum repetitive peak isolation voltage (VDE) | VIORM | 565 | V 峰值 | DIN VDE V 0884-10; π12xM3x | 9 | ||
| Maximum safety temperature | TS | 150 | ℃ | safety limit values; π12xM3x | 9 | ||
| Maximum power dissipation at 25℃ (safety) | PS | 1.25 | W | 25℃; π12xM3x | 9 | ||
| Junction-to-air thermal resistance | θJA | 100 | °C/W | thermocouple at package bottom center; π12xM3x | 8 |
CAD (KiCad official)
- Symbol:
π121M30 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
121m30-etched.step/121m30-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);121m30.step/121m30.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 2Pai Semi datasheet (18 pp, sha256
1236ebd83e9a55d1, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# π121M30
**2Pai Semi** · Digital Isolators · SOP-8
π121M30 from 2Pai Semi, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Primary-side isolator supply, which operates from 3.0 V to 5.5 V and should be bypassed to GND1 with a low-ESR ceramic capacitor of 0.1 µF to 10 µF placed as close to the device as possible. |
| 2 | VIA | input | Channel A input on the primary side; logic high requires at least 0.7×VDD1 and logic low is at most 0.3×VDD1, with the absolute maximum input range of −0.5 V to VDD1 + 0.5 V. |
| 3 | VOB | output | Channel B output on the secondary side, rated for IOH of −6 mA and IOL of 6 mA under recommended conditions, with absolute maximum output voltage of −0.5 V to VDD2 + 0.5 V; the π121M30 default output level is Low when the input side is unpowered. |
| 4 | GND1 | power_in | Primary-side ground reference for VDD1 and the channel A and B inputs. |
| 5 | GND2 | power_in | Secondary-side ground reference for VDD2 and the channel A and B outputs, rated for 3000 Vrms isolation for 1 minute with GND1. |
| 6 | VIB | input | Channel B input on the primary side; logic high requires at least 0.7×VDD1 and logic low is at most 0.3×VDD1, with the absolute maximum input range of −0.5 V to VDD1 + 0.5 V. |
| 7 | VOA | output | Channel A output on the secondary side, rated for IOH of −6 mA and IOL of 6 mA under recommended conditions, with absolute maximum output voltage of −0.5 V to VDD2 + 0.5 V. |
| 8 | VDD2 | power_in | Secondary-side isolator supply, which operates from 3.0 V to 5.5 V and should be bypassed to GND2 with a low-ESR ceramic capacitor of 0.1 µF to 10 µF. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOP-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDDx | 3 | | 5.5 | V | | 4 |
| Supply voltage (absolute maximum) | VDD1-GND1, VDD2-GND2 | -0.5 | | 7 | V | | 3 |
| Input signal voltage | VIA, VIB | -0.5 | | | V | upper limit printed as VDDx + 0.5 V | 3 |
| Output voltage | VOA, VOB | -0.5 | | | V | upper limit printed as VDDx + 0.5 V | 3 |
| Primary per-channel average output current | IO1 | -10 | | 10 | mA | | 3 |
| Secondary per-channel average output current | IO2 | -10 | | 10 | mA | | 3 |
| Common-mode transient immunity | CMTI | -200 | | 200 | kV/µs | | 3 |
| Storage temperature range | TST | -65 | | 150 | ℃ | | 3 |
| Operating ambient temperature range (absolute maximum) | TA | -40 | | 125 | ℃ | | 3 |
| Input signal low level | VIL | 0 | | | V | upper limit printed as 0.3*VDDx1 V | 4 |
| High-level output current | IOH | | | -6 | mA | output high | 4 |
| Low-level output current | IOL | | | 6 | mA | output low | 4 |
| Communication rate | | 0 | | 10 | Mbps | | 4 |
| Junction temperature | TJ | -40 | | 150 | ℃ | | 4 |
| Ambient temperature | TA | -40 | | 125 | ℃ | | 4 |
| Minimum pulse width | PW | 100 | | | ns | within pulse width distortion (PWD) limit | 4 |
| Maximum data rate | | | | 10 | Mbps | within pulse width distortion (PWD) limit | 4 |
| Propagation delay tpHL, tpLH (5VDC supply) | tpHL, tpLH | 5.5 | 8 | 12.5 | ns | 5VDC supply | 4 |
| Propagation delay tpHL, tpLH (3.3VDC supply) | tpHL, tpLH | 6.5 | 9 | 13.5 | ns | 3.3VDC supply | 4 |
| Pulse width distortion (5VDC supply) | PWD | | 0.3 | 3 | ns | 5VDC supply; max difference between tpHL and tpLH | 4 |
| Pulse width distortion (3.3VDC supply) | PWD | | 0.4 | 3 | ns | 3.3VDC supply; max difference between tpHL and tpLH | 4 |
| Low-level output voltage | VOL | 0 | | 0.1 | V | 20 µA output current | 6 |
| Low-level output voltage | VOL | 0.1 | | 0.2 | V | 2 mA output current | 6 |
| Input current per channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ signal voltage ≤ VDDx1 | 6 |
| VDDx1 undervoltage threshold (rising) | VDDxUV+ | 2.45 | 2.75 | 2.95 | V | | 6 |
| VDDx1 undervoltage threshold (falling) | VDDxUV- | 2.3 | 2.6 | 2.75 | V | | 6 |
| Quiescent supply current IDD1 (5VDC, input low) | IDD1 (Q) | 0.42 | 0.52 | 0.68 | mA | 5VDC; π12xMx0 input low 0V | 6 |
| Quiescent supply current IDD2 (5VDC, x1 input high) | IDD2 (Q) | 0.42 | 0.52 | 0.68 | mA | 5VDC; π12xMx1 input high 5V | 6 |
| Quiescent supply current IDD1 (5VDC, input high) | IDD1 (Q) | 0.44 | 0.55 | 0.71 | mA | 5VDC; π12xMx0 input high 5V | 6 |
| Quiescent supply current IDD2 (5VDC, x1 input low) | IDD2 (Q) | 0.44 | 0.55 | 0.71 | mA | 5VDC; π12xMx1 input low 0V | 6 |
| Quiescent supply current IDD1 (3.3VDC, input low) | IDD1 (Q) | 0.41 | 0.52 | 0.67 | mA | 3.3VDC; π12xMx0 input low 0V | 6 |
| Quiescent supply current IDD2 (3.3VDC, x1 input high) | IDD2 (Q) | 0.41 | 0.52 | 0.67 | mA | 3.3VDC; π12xMx1 input high 3.3V | 6 |
| Quiescent supply current IDD1 (3.3VDC, input high) | IDD1 (Q) | 0.41 | 0.51 | 0.66 | mA | 3.3VDC; π12xMx0 input high 3.3V | 7 |
| Quiescent supply current IDD2 (3.3VDC, x1 input low) | IDD2 (Q) | 0.41 | 0.51 | 0.66 | mA | 3.3VDC; π12xMx1 input low 0V | 7 |
| Total supply current IDD1 at 150 Kbps (5VDC) | IDD1 | | 0.54 | 0.81 | mA | CL=0pF; 150 Kbps; 5VDC | 7 |
| Total supply current IDD1 at 1 Mbps (5VDC) | IDD1 | | 0.58 | 0.86 | mA | CL=0pF; 1 Mbps; 5VDC | 7 |
| Total supply current IDD1 at 10 Mbps (5VDC) | IDD1 | | 0.97 | 1.46 | mA | CL=0pF; 10 Mbps; 5VDC | 7 |
| Total supply current IDD2 at 150 Kbps (5VDC) | IDD2 | | 0.54 | 0.81 | mA | CL=0pF; 150 Kbps; 5VDC | 7 |
| Total supply current IDD2 at 1 Mbps (5VDC) | IDD2 | | 0.58 | 0.86 | mA | CL=0pF; 1 Mbps; 5VDC | 7 |
| Total supply current IDD2 at 10 Mbps (5VDC) | IDD2 | | 0.97 | 1.46 | mA | CL=0pF; 10 Mbps; 5VDC | 7 |
| Total supply current IDD1 at 150 Kbps (3.3VDC) | IDD1 | | 0.52 | 0.78 | mA | CL=0pF; 150 Kbps; 3.3VDC | 7 |
| Total supply current IDD1 at 1 Mbps (3.3VDC) | IDD1 | | 0.54 | 0.81 | mA | CL=0pF; 1 Mbps; 3.3VDC | 7 |
| Total supply current IDD1 at 10 Mbps (3.3VDC) | IDD1 | | 0.77 | 1.16 | mA | CL=0pF; 10 Mbps; 3.3VDC | 7 |
| Total supply current IDD2 at 150 Kbps (3.3VDC) | IDD2 | | 0.52 | 0.78 | mA | CL=0pF; 150 Kbps; 3.3VDC | 7 |
| Total supply current IDD2 at 1 Mbps (3.3VDC) | IDD2 | | 0.54 | 0.81 | mA | CL=0pF; 1 Mbps; 3.3VDC | 7 |
| Total supply current IDD2 at 10 Mbps (3.3VDC) | IDD2 | | 0.77 | 1.16 | mA | CL=0pF; 10 Mbps; 3.3VDC | 7 |
| Rated isolation voltage | | | | 3000 | Vrms | 1 minute; π12xM3x | 8 |
| Maximum repetitive peak isolation voltage (VDE) | VIORM | | | 565 | V 峰值 | DIN VDE V 0884-10; π12xM3x | 9 |
| Maximum safety temperature | TS | | | 150 | ℃ | safety limit values; π12xM3x | 9 |
| Maximum power dissipation at 25℃ (safety) | PS | | | 1.25 | W | 25℃; π12xM3x | 9 |
| Junction-to-air thermal resistance | θJA | | 100 | | °C/W | thermocouple at package bottom center; π12xM3x | 8 |
## CAD (KiCad official)
- Symbol: `π121M30`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `121m30-etched.step` / `121m30-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `121m30.step` / `121m30.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [2Pai Semi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590207921221885952) (18 pp, sha256 `1236ebd83e9a55d1`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/121m30-datasheet.pdf)