component
π121E31
Public Made by Adomby adom
2Pai Semi Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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π121E31
2Pai Semi · Digital Isolators · SOIC-8
π121E31 from 2Pai Semi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, 3.0 V to 5.5 V operating range, bypass with 0.1 µF to 10 µF to GND1. |
| 2 | VIA | input | Logic input A on side 1; input must be low when VDD1 is unpowered, and open input gives default output. |
| 3 | VOB | output | Logic output B on side 2 (VDD2 domain), rated for ±6 mA recommended output current. |
| 4 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 5 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 6 | VIB | input | Logic input B on side 2 (VDD2 domain); input must be low when VDD2 is unpowered. |
| 7 | VOA | output | Logic output A on side 1 (VDD1 domain), rated for ±6 mA recommended output current. |
| 8 | VDD2 | power_in | Supply voltage for isolator side 2, 3.0 V to 5.5 V operating range, bypass with 0.1 µF to 10 µF to GND2. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD1-GND1, VDD2-GND2 | -0.5 | 7 | V | TA = 25°C | 3 | |
| Input Voltage | VIA, VIB | -0.5 | V | -0.5 V to VDDx + 0.5 V | 3 | ||
| Output Voltage | VOA, VOB | -0.5 | V | -0.5 V to VDDx + 0.5 V | 3 | ||
| Average Output Current per Pin, Side 1 | IO1 | -10 | 10 | mA | 3 | ||
| Average Output Current per Pin, Side 2 | IO2 | -10 | 10 | mA | 3 | ||
| Common-Mode Transients Immunity | -200 | 200 | kV/µs | 3 | |||
| Storage Temperature | TST | -65 | 150 | °C | 3 | ||
| Ambient Operating Temperature | TA | -40 | 125 | °C | 3 | ||
| Supply Voltage | VDDx | 3 | 5.5 | V | 4 | ||
| High Level Output Current | IOH | -6 | mA | 4 | |||
| Low Level Output Current | IOL | 6 | mA | 4 | |||
| Data Rate | 0 | 200 | Mbps | 4 | |||
| Junction Temperature | TJ | -40 | 150 | °C | 4 | ||
| Ambient Operating Temperature | TA | -40 | 125 | °C | 4 | ||
| Minimum Pulse Width | PW | 5 | ns | Within pulse width distortion (PWD) limit | 4 | ||
| Maximum Data Rate | 200 | Mbps | Within PWD limit | 4 | |||
| Propagation Delay Time | tpHL, tpLH | 5.5 | 8 | 12.5 | ns | @ 5VDC supply | 4 |
| Propagation Delay Time | tpHL, tpLH | 6.5 | 9 | 13.5 | ns | @ 3.3VDC supply | 4 |
| Pulse Width Distortion | PWD | 0.3 | 3 | ns | /tpHL - tpLH/ @ 5VDC supply | 4 | |
| Pulse Width Distortion | PWD | 0.4 | 3 | ns | /tpHL - tpLH/ @ 3.3VDC supply | 4 | |
| Part to Part Propagation Delay Skew | tPSK | 2 | ns | @ 5VDC supply | 5 | ||
| Channel to Channel Propagation Delay Skew | tCSK | 1.8 | ns | @ 5VDC supply | 5 | ||
| Channel to Channel Propagation Delay Skew | tCSK | 2 | ns | @ 3.3VDC supply | 5 | ||
| Output Signal Rise/Fall Time | tr/tf | 1.5 | ns | See Figure 13. | 5 | ||
| Dynamic Input Supply Current per Channel | IDDI (D) | 9 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC Supply | 5 | ||
| Dynamic Output Supply Current per Channel | IDDO (D) | 38 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC Supply | 5 | ||
| Dynamic Input Supply Current per Channel | IDDI (D) | 5 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC Supply | 5 | ||
| Dynamic Output Supply Current per Channel | IDDO (D) | 23 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC Supply | 5 | ||
| Common-Mode Transient Immunity | CMTI | 75 | kV/µs | VIN = VDDx or 0V, VCM = 1000 V. | 5 | ||
| Jitter | 120 | ps p-p | See the Jitter Measurement section | 5 | |||
| Jitter | 20 | ps rms | See the Jitter Measurement section | 5 | |||
| ESD (HBM) | ESD | 8 | kV | Human body model, ±8 kV | 5 | ||
| Low Level Output Voltage | VOL | 0 | 0.1 | V | 20 µA output current | 6 | |
| Low Level Output Voltage | VOL | 0.1 | 0.2 | V | 2 mA output current | 6 | |
| Input Current per Signal Channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ Signal voltage ≤ VDDX | 6 |
| VDDx Undervoltage Rising Threshold | VDDxUV+ | 2.45 | 2.75 | 2.95 | V | 6 | |
| VDDx Undervoltage Falling Threshold | VDDxUV− | 2.3 | 2.6 | 2.75 | V | 6 | |
| VDDx Hysteresis | VDDxUVH | 0.15 | V | 6 | |||
| Quiescent Supply Current Side 1 | IDD1 (Q) | 0.42 | 0.52 | 0.68 | mA | 5VDC; VI=0V for π12xEx0 | 7 |
| Quiescent Supply Current Side 2 | IDD2 (Q) | 0.42 | 0.52 | 0.68 | mA | 5VDC; VI=5V for π12xEx1 | 7 |
| Quiescent Supply Current Side 1 | IDD1 (Q) | 0.44 | 0.55 | 0.71 | mA | 5VDC; VI=5V for π12xEx0 | 7 |
| Quiescent Supply Current Side 2 | IDD2 (Q) | 0.44 | 0.55 | 0.71 | mA | 5VDC; VI=0V for π12xEx1 | 7 |
| Quiescent Supply Current Side 1 | IDD1 (Q) | 0.41 | 0.52 | 0.67 | mA | 3.3VDC; VI=0V for π12xEx0 | 7 |
| Quiescent Supply Current Side 2 | IDD2 (Q) | 0.41 | 0.52 | 0.67 | mA | 3.3VDC; VI=3.3V for π12xEx1 | 7 |
| Quiescent Supply Current Side 1 | IDD1 (Q) | 0.41 | 0.51 | 0.66 | mA | 3.3VDC; VI=3.3V for π12xEx0 | 7 |
| Quiescent Supply Current Side 2 | IDD2 (Q) | 0.41 | 0.51 | 0.66 | mA | 3.3VDC; VI=0V for π12xEx1 | 7 |
| Supply Current IDD1/IDD2 at 2 Mbps | IDD1, IDD2 | 0.64 | 1.02 | mA | 5VDC; CL = 0 pF | 8 | |
| Supply Current IDD1/IDD2 at 20 Mbps | IDD1, IDD2 | 1.94 | 3.1 | mA | 5VDC; CL = 0 pF | 8 | |
| Supply Current IDD1/IDD2 at 200 Mbps | IDD1, IDD2 | 10.4 | 16.64 | mA | 5VDC; CL = 0 pF | 8 | |
| Supply Current IDD1/IDD2 at 2 Mbps | IDD1, IDD2 | 0.59 | 0.95 | mA | 3.3VDC; CL = 0 pF | 8 | |
| Supply Current IDD1/IDD2 at 20 Mbps | IDD1, IDD2 | 1.54 | 2.46 | mA | 3.3VDC; CL = 0 pF | 8 | |
| Supply Current IDD1/IDD2 at 200 Mbps | IDD1, IDD2 | 6.58 | 10.53 | mA | 3.3VDC; CL = 0 pF | 8 | |
| Rated Dielectric Insulation Voltage | 3000 | V rms | 1-minute duration | 8 | |||
| IC Junction to Ambient Thermal Resistance | θJA | 100 | °C/W | Thermocouple located at center of package underside | 9 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN V VDE V 0884-11, each π120E3x/π121E3x/π122E3x is proof tested by applying an insulation test voltage ≥ 848 V peak for 1 sec (partial discharge detection limit = 5 pC); each π120 | 9 |
CAD (KiCad official)
- Symbol:
π121E31 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
121e31-etched.step/121e31-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);121e31.step/121e31.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 2Pai Semi datasheet (18 pp, sha256
46f1f75769a4de29, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# π121E31
**2Pai Semi** · Digital Isolators · SOIC-8
π121E31 from 2Pai Semi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, 3.0 V to 5.5 V operating range, bypass with 0.1 µF to 10 µF to GND1. |
| 2 | VIA | input | Logic input A on side 1; input must be low when VDD1 is unpowered, and open input gives default output. |
| 3 | VOB | output | Logic output B on side 2 (VDD2 domain), rated for ±6 mA recommended output current. |
| 4 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 5 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 6 | VIB | input | Logic input B on side 2 (VDD2 domain); input must be low when VDD2 is unpowered. |
| 7 | VOA | output | Logic output A on side 1 (VDD1 domain), rated for ±6 mA recommended output current. |
| 8 | VDD2 | power_in | Supply voltage for isolator side 2, 3.0 V to 5.5 V operating range, bypass with 0.1 µF to 10 µF to GND2. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD1-GND1, VDD2-GND2 | -0.5 | | 7 | V | TA = 25°C | 3 |
| Input Voltage | VIA, VIB | -0.5 | | | V | -0.5 V to VDDx + 0.5 V | 3 |
| Output Voltage | VOA, VOB | -0.5 | | | V | -0.5 V to VDDx + 0.5 V | 3 |
| Average Output Current per Pin, Side 1 | IO1 | -10 | | 10 | mA | | 3 |
| Average Output Current per Pin, Side 2 | IO2 | -10 | | 10 | mA | | 3 |
| Common-Mode Transients Immunity | | -200 | | 200 | kV/µs | | 3 |
| Storage Temperature | TST | -65 | | 150 | °C | | 3 |
| Ambient Operating Temperature | TA | -40 | | 125 | °C | | 3 |
| Supply Voltage | VDDx | 3 | | 5.5 | V | | 4 |
| High Level Output Current | IOH | -6 | | | mA | | 4 |
| Low Level Output Current | IOL | | | 6 | mA | | 4 |
| Data Rate | | 0 | | 200 | Mbps | | 4 |
| Junction Temperature | TJ | -40 | | 150 | °C | | 4 |
| Ambient Operating Temperature | TA | -40 | | 125 | °C | | 4 |
| Minimum Pulse Width | PW | | | 5 | ns | Within pulse width distortion (PWD) limit | 4 |
| Maximum Data Rate | | 200 | | | Mbps | Within PWD limit | 4 |
| Propagation Delay Time | tpHL, tpLH | 5.5 | 8 | 12.5 | ns | @ 5VDC supply | 4 |
| Propagation Delay Time | tpHL, tpLH | 6.5 | 9 | 13.5 | ns | @ 3.3VDC supply | 4 |
| Pulse Width Distortion | PWD | | 0.3 | 3 | ns | /tpHL - tpLH/ @ 5VDC supply | 4 |
| Pulse Width Distortion | PWD | | 0.4 | 3 | ns | /tpHL - tpLH/ @ 3.3VDC supply | 4 |
| Part to Part Propagation Delay Skew | tPSK | | | 2 | ns | @ 5VDC supply | 5 |
| Channel to Channel Propagation Delay Skew | tCSK | | | 1.8 | ns | @ 5VDC supply | 5 |
| Channel to Channel Propagation Delay Skew | tCSK | | | 2 | ns | @ 3.3VDC supply | 5 |
| Output Signal Rise/Fall Time | tr/tf | | 1.5 | | ns | See Figure 13. | 5 |
| Dynamic Input Supply Current per Channel | IDDI (D) | | 9 | | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC Supply | 5 |
| Dynamic Output Supply Current per Channel | IDDO (D) | | 38 | | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC Supply | 5 |
| Dynamic Input Supply Current per Channel | IDDI (D) | | 5 | | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC Supply | 5 |
| Dynamic Output Supply Current per Channel | IDDO (D) | | 23 | | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC Supply | 5 |
| Common-Mode Transient Immunity | CMTI | | 75 | | kV/µs | VIN = VDDx or 0V, VCM = 1000 V. | 5 |
| Jitter | | | 120 | | ps p-p | See the Jitter Measurement section | 5 |
| Jitter | | | 20 | | ps rms | See the Jitter Measurement section | 5 |
| ESD (HBM) | ESD | | 8 | | kV | Human body model, ±8 kV | 5 |
| Low Level Output Voltage | VOL | | 0 | 0.1 | V | 20 µA output current | 6 |
| Low Level Output Voltage | VOL | | 0.1 | 0.2 | V | 2 mA output current | 6 |
| Input Current per Signal Channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ Signal voltage ≤ VDDX | 6 |
| VDDx Undervoltage Rising Threshold | VDDxUV+ | 2.45 | 2.75 | 2.95 | V | | 6 |
| VDDx Undervoltage Falling Threshold | VDDxUV− | 2.3 | 2.6 | 2.75 | V | | 6 |
| VDDx Hysteresis | VDDxUVH | | 0.15 | | V | | 6 |
| Quiescent Supply Current Side 1 | IDD1 (Q) | 0.42 | 0.52 | 0.68 | mA | 5VDC; VI=0V for π12xEx0 | 7 |
| Quiescent Supply Current Side 2 | IDD2 (Q) | 0.42 | 0.52 | 0.68 | mA | 5VDC; VI=5V for π12xEx1 | 7 |
| Quiescent Supply Current Side 1 | IDD1 (Q) | 0.44 | 0.55 | 0.71 | mA | 5VDC; VI=5V for π12xEx0 | 7 |
| Quiescent Supply Current Side 2 | IDD2 (Q) | 0.44 | 0.55 | 0.71 | mA | 5VDC; VI=0V for π12xEx1 | 7 |
| Quiescent Supply Current Side 1 | IDD1 (Q) | 0.41 | 0.52 | 0.67 | mA | 3.3VDC; VI=0V for π12xEx0 | 7 |
| Quiescent Supply Current Side 2 | IDD2 (Q) | 0.41 | 0.52 | 0.67 | mA | 3.3VDC; VI=3.3V for π12xEx1 | 7 |
| Quiescent Supply Current Side 1 | IDD1 (Q) | 0.41 | 0.51 | 0.66 | mA | 3.3VDC; VI=3.3V for π12xEx0 | 7 |
| Quiescent Supply Current Side 2 | IDD2 (Q) | 0.41 | 0.51 | 0.66 | mA | 3.3VDC; VI=0V for π12xEx1 | 7 |
| Supply Current IDD1/IDD2 at 2 Mbps | IDD1, IDD2 | | 0.64 | 1.02 | mA | 5VDC; CL = 0 pF | 8 |
| Supply Current IDD1/IDD2 at 20 Mbps | IDD1, IDD2 | | 1.94 | 3.1 | mA | 5VDC; CL = 0 pF | 8 |
| Supply Current IDD1/IDD2 at 200 Mbps | IDD1, IDD2 | | 10.4 | 16.64 | mA | 5VDC; CL = 0 pF | 8 |
| Supply Current IDD1/IDD2 at 2 Mbps | IDD1, IDD2 | | 0.59 | 0.95 | mA | 3.3VDC; CL = 0 pF | 8 |
| Supply Current IDD1/IDD2 at 20 Mbps | IDD1, IDD2 | | 1.54 | 2.46 | mA | 3.3VDC; CL = 0 pF | 8 |
| Supply Current IDD1/IDD2 at 200 Mbps | IDD1, IDD2 | | 6.58 | 10.53 | mA | 3.3VDC; CL = 0 pF | 8 |
| Rated Dielectric Insulation Voltage | | | 3000 | | V rms | 1-minute duration | 8 |
| IC Junction to Ambient Thermal Resistance | θJA | | 100 | | °C/W | Thermocouple located at center of package underside | 9 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | | In accordance with DIN V VDE V 0884-11, each π120E3x/π121E3x/π122E3x is proof tested by applying an insulation test voltage ≥ 848 V peak for 1 sec (partial discharge detection limit = 5 pC); each π120 | 9 |
## CAD (KiCad official)
- Symbol: `π121E31`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `121e31-etched.step` / `121e31-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `121e31.step` / `121e31.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [2Pai Semi datasheet](docs/121e31-datasheet.pdf) (18 pp, sha256 `46f1f75769a4de29`, retrieved 2026-10-22, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/121e31-datasheet.pdf)