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π120M31
Public Made by Adomby adom
2Pai Semi Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 3d ago |
| viewers | 3d ago |
| 120m31-etched.glb | 3d ago |
| 120m31-etched.step | 3d ago |
| 120m31-hero.glb | 3d ago |
| 120m31-hero.overlay.json | 3d ago |
| 120m31.glb | 3d ago |
| 120m31.kicad_mod | 3d ago |
| 120m31.kicad_sym | 3d ago |
| 120m31.lbr | 3d ago |
| 120m31.step | 3d ago |
| package.json | 3d ago |
| page.json | 3d ago |
| README.md | 3d ago |
π120M31
2Pai Semi · Digital Isolators · SOIC-8
π120M31 from 2Pai Semi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, specified for 3.0 V to 5.5 V; side 1 is treated as unpowered below 2.3 V and powered at 2.9 V or above. |
| 2 | VIA | input | Logic input A, referenced to side 1 supply VDD1, with VIH of 0.7×VDD1 minimum and VIL of 0.3×VDD1 maximum. |
| 3 | VIB | input | Logic input B, referenced to side 1 supply VDD1, with VIH of 0.7×VDD1 minimum and VIL of 0.3×VDD1 maximum. |
| 4 | GND1 | power_in | Ground 1, the ground reference for isolator side 1 (VDD1 side). |
| 5 | GND2 | power_in | Ground 2, the ground reference for isolator side 2 (VDD2 side); isolated from GND1. |
| 6 | VOB | output | Logic output B on isolator side 2, driven from the side 2 supply VDD2 with a rated average output current of −10 mA to +10 mA. |
| 7 | VOA | output | Logic output A on isolator side 2, driven from the side 2 supply VDD2 with a rated average output current of −10 mA to +10 mA. |
| 8 | VDD2 | power_in | Supply voltage for isolator side 2, specified for 3.0 V to 5.5 V; side 2 is treated as unpowered below 2.3 V and powered at 2.9 V or above. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltages (VDD1-GND1, VDD2-GND2) | -0.5 | 7 | V | 4 | |||
| Input Voltages (VIA, VIB) | -0.5 | V | 4 | ||||
| Output Voltages (VOA, VOB) | -0.5 | V | 4 | ||||
| Average Output Current per Pin, Side 1 | IO1 | -10 | 10 | mA | 4 | ||
| Average Output Current per Pin, Side 2 | IO2 | -10 | 10 | mA | 4 | ||
| Common-Mode Transients Immunity | -150 | 150 | kV/µs | 4 | |||
| Storage Temperature (TST) Range | TST | -65 | 150 | °C | 4 | ||
| Ambient Operating Temperature (TA) Range | TA | -40 | 125 | °C | 4 | ||
| Supply Voltage | VDDx | 3 | 5.5 | V | 4 | ||
| Low Level Input Signal Voltage | VIL | 0 | V | 4 | |||
| High Level Output Current | IOH | -6 | mA | 4 | |||
| Low Level Output Current | IOL | 6 | mA | 4 | |||
| Maximum Data Rate | 0 | 10 | Mbps | 4 | |||
| Junction Temperature | TJ | -40 | 150 | °C | 4 | ||
| Ambient Operating Temperature | TA | -40 | 125 | °C | 4 | ||
| Minimum Pulse Width | PW | 100 | ns | Within pulse width distortion (PWD) limit | 5 | ||
| Maximum Data Rate (Table 4) | 10 | Mbps | Within PWD limit | 5 | |||
| Propagation Delay Time (5 V) | tpHL, tpLH | 5.5 | 8 | 12.5 | ns | 50% input to 50% output; 50% @ 5VDC supply | 5 |
| Propagation Delay Time (3.3 V) | tpHL, tpLH | 6.5 | 9 | 13.5 | ns | 50% input to 50% output @ 3.3VDC supply | 5 |
| Pulse Width Distortion (5 V) | PWD | 0 | 0.3 | 0.8 | ns | /tpHL - tpLH/ @ 5VDC supply | 5 |
| Pulse Width Distortion (3.3 V) | PWD | 0 | 0.3 | 0.8 | ns | /tpHL - tpLH/ @ 3.3VDC supply | 5 |
| Part to Part Propagation Delay Skew (5 V) | tPSK | 1 | ns | @ 5VDC supply; max difference between any two devices at same temperature, load and voltage | 5 | ||
| Part to Part Propagation Delay Skew (3.3 V) | tPSK | 1 | ns | @ 3.3VDC supply | 5 | ||
| Channel to Channel Propagation Delay Skew (5 V) | tCSK | 0 | 1 | ns | @ 5VDC supply | 5 | |
| Channel to Channel Propagation Delay Skew (3.3 V) | tCSK | 0 | 0.8 | ns | @ 3.3VDC supply | 5 | |
| Output Signal Rise/Fall Time | tr/tf | 1.5 | ns | 10% to 90% signal terminated 50 | 5 | ||
| Common-Mode Transient Immunity | CMTI | 75 | kV/µs | VIN = VDDx or 0V, VCM = 1000 V | 5 | ||
| ESD (HBM - Human body model) | ESD | -8 | 8 | kV | All pins | 5 | |
| Low Level Output Voltage (20 µA) | VOL | 0 | 0.1 | V | 20 µA output current | 6 | |
| Low Level Output Voltage (2 mA) | VOL | 0.1 | 0.2 | V | 2 mA output current | 6 | |
| Input Current per Signal Channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ Signal voltage ≤ VDDX1 | 6 |
| VDDx1 Undervoltage Rising Threshold | VDDxUV+ | 2.45 | 2.65 | 2.9 | V | 6 | |
| VDDx1 Undervoltage Falling Threshold | VDDxUV− | 2.3 | 2.5 | 2.75 | V | 6 | |
| Quiescent Supply Current, side 1 | IDD1 (Q) | 64 | 80 | 104 | µA | @ 5VDC Supply; 0V input signal | 6 |
| Quiescent Supply Current, side 2 | IDD2 (Q) | 781 | 976 | 1269 | µA | @ 5VDC Supply; 0V input signal | 6 |
| Quiescent Supply Current, side 1 | IDD1 (Q) | 158 | 197 | 256 | µA | @ 5VDC Supply; 5V input signal | 6 |
| Quiescent Supply Current, side 2 | IDD2 (Q) | 738 | 923 | 1200 | µA | @ 5VDC Supply; 5V input signal | 6 |
| Quiescent Supply Current, side 1 | IDD1 (Q) | 63 | 79 | 103 | µA | @ 3.3VDC Supply; 0V input signal | 6 |
| Quiescent Supply Current, side 2 | IDD2 (Q) | 772 | 965 | 1255 | µA | @ 3.3VDC Supply; 0V input signal | 6 |
| Total Supply Current side 1 (150 Kbps, 5 V) | IDD1 | 0.14 | 0.21 | mA | 150 Kbps; @5VDC supply; CL = 0 pF | 7 | |
| Total Supply Current side 2 (150 Kbps, 5 V) | IDD2 | 0.95 | 1.43 | mA | 150 Kbps; @5VDC supply; CL = 0 pF | 7 | |
| Total Supply Current side 1 (1 Mbps, 5 V) | IDD1 | 0.15 | 0.22 | mA | 1 Mbps; @5VDC supply; CL = 0 pF | 7 | |
| Total Supply Current side 2 (1 Mbps, 5 V) | IDD2 | 1.02 | 1.52 | mA | 1 Mbps; @5VDC supply; CL = 0 pF | 7 | |
| Total Supply Current side 1 (10 Mbps, 5 V) | IDD1 | 0.24 | 0.36 | mA | 10 Mbps; @5VDC supply; CL = 0 pF | 7 | |
| Total Supply Current side 2 (10 Mbps, 5 V) | IDD2 | 1.76 | 2.63 | mA | 10 Mbps; @5VDC supply; CL = 0 pF | 7 | |
| Total Supply Current side 1 (150 Kbps, 3.3 V) | IDD1 | 0.11 | 0.17 | mA | 150 Kbps; @3.3VDC supply; CL = 0 pF | 7 | |
| Total Supply Current side 2 (150 Kbps, 3.3 V) | IDD2 | 0.93 | 1.4 | mA | 150 Kbps; @3.3VDC supply; CL = 0 pF | 7 | |
| Total Supply Current side 1 (1 Mbps, 3.3 V) | IDD1 | 0.12 | 0.17 | mA | 1 Mbps; @3.3VDC supply; CL = 0 pF | 7 | |
| Total Supply Current side 2 (1 Mbps, 3.3 V) | IDD2 | 0.97 | 1.46 | mA | 1 Mbps; @3.3VDC supply; CL = 0 pF | 7 | |
| Total Supply Current side 1 (10 Mbps, 3.3 V) | IDD1 | 0.18 | 0.27 | mA | 10 Mbps; @3.3VDC supply; CL = 0 pF | 7 | |
| Total Supply Current side 2 (10 Mbps, 3.3 V) | IDD2 | 1.43 | 2.14 | mA | 10 Mbps; @3.3VDC supply; CL = 0 pF | 7 | |
| Minimum External Air Gap (Clearance) | L (CLR) | 4 | mm | Measured from input terminals to output terminals, shortest distance through air | 7 | ||
| Minimum External Tracking (Creepage) | L (CRP) | 4 | mm | Measured from input terminals to output terminals, shortest distance path along body | 7 | ||
| Minimum Internal Gap (Internal Clearance) | 11 | µm | Insulation distance through insulation | 7 | |||
| Tracking Resistance (Comparative Tracking Index) | CTI | 400 | V | DIN IEC 112/VDE 0303 Part 1 (printed as '>400') | 7 | ||
| IC Junction to Ambient Thermal Resistance | θJA | 100 | °C/W | Thermocouple located at center of package underside | 7 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN V VDE V 0884-10, each π120M3x/π121M3x/π122M3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial discharge detection limit = 5 pC); each π12 | 8 |
CAD (KiCad official)
- Symbol:
π120M31 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
120m31-etched.step/120m31-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);120m31.step/120m31.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 2Pai Semi datasheet (15 pp, sha256
4fbbd7bc7c4e10cc, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).