π120E30

{
  "schema_version": 1,
  "type": "component",
  "slug": "120e30",
  "title": "π120E30",
  "brief": "2Pai Semi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-N. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.3",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "pmic",
    "π120e30"
  ],
  "component": {
    "mpn": "π120E30",
    "manufacturer": "2Pai Semi",
    "package": "SOIC-8-N",
    "pin_count": 8,
    "category": "PMIC",
    "subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",
    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2306281036_2Pai-Semi--120E30_C970948.pdf",
    "parts": {
      "symbol": "120e30.kicad_sym",
      "footprint": "120e30.kicad_mod",
      "model_3d": "120e30-hero.glb",
      "model_3d_plain": "120e30.glb",
      "model_3d_step": "120e30-etched.step",
      "model_3d_step_plain": "120e30.step",
      "lbr": "120e30.lbr"
    },
    "distributor_links": {
      "lcsc": "C970948"
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD1",
        "type": "power_in",
        "description": "Supply voltage for isolator Side 1. 3.0 V to 5.5 V operating range; 2.75 V typical undervoltage lockout rising threshold. Bypass to GND1 with 0.1 µF-10 µF low-ESR ceramic close to the pin."
      },
      {
        "number": "2",
        "name": "VIA",
        "type": "input",
        "description": "Logic input for channel A (Side 1). CMOS input, VIH ≥ 0.7·VDD1, VIL ≤ 0.3·VDD1. Absolute max −0.5 V to VDD1 + 0.5 V. Drives isolated logic output VOA on Side 2."
      },
      {
        "number": "3",
        "name": "VIB",
        "type": "input",
        "description": "Logic input for channel B (Side 1). CMOS input, VIH ≥ 0.7·VDD1, VIL ≤ 0.3·VDD1. Drives isolated logic output VOB on Side 2. Both π120 channels are forward (Side 1 → Side 2)."
      },
      {
        "number": "4",
        "name": "GND1",
        "type": "power_in",
        "description": "Ground reference for isolator Side 1. Return for VDD1 bypass and for VIA/VIB input signals. Isolated from GND2 across the on-die iDivider capacitive barrier."
      },
      {
        "number": "5",
        "name": "GND2",
        "type": "power_in",
        "description": "Ground reference for isolator Side 2. Return for VDD2 bypass and for VOA/VOB output signals. Isolated from GND1 (3.0 kVrms withstand for the E3x variant)."
      },
      {
        "number": "6",
        "name": "VOB",
        "type": "output",
        "description": "Logic output for channel B (Side 2), mirrors VIB across the isolation barrier. Push-pull CMOS output rated ±10 mA absolute max, recommended ±6 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix)."
      },
      {
        "number": "7",
        "name": "VOA",
        "type": "output",
        "description": "Logic output for channel A (Side 2), mirrors VIA across the isolation barrier. Push-pull CMOS output rated ±10 mA absolute max, recommended ±6 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix)."
      },
      {
        "number": "8",
        "name": "VDD2",
        "type": "power_in",
        "description": "Supply voltage for isolator Side 2. 3.0 V to 5.5 V; independent of VDD1 so this pin performs the 3 V ↔ 5 V level translation. Bypass to GND2 with 0.1 µF-10 µF low-ESR ceramic close to the pin."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2306281036_2Pai-Semi--120E30_C970948.pdf",
        "pages": 18,
        "sha256": "46f1f75769a4de29",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -1.905
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",
      "mark": "drawn"
    },
    "models_3d": [
      {
        "file": "120e30.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "120e30-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "30dc1692d1919765633ea0deebdac262aa27c21078e2092553a506a4a0e15bdc",
        "checked": "2026-11-12",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "characteristics": {
      "version": 1,
      "source": "datasheet",
      "rows": [
        {
          "name": "Output current",
          "symbol": "IOUT",
          "kind": "recommended_operating",
          "unit": "mA",
          "min": -10,
          "typ": null,
          "max": -6,
          "conditions": "datasheet prints several: -6 mA (High Level Output Current), 6 mA (Low Level Output Current), 10 mA (Average Output Current per Pin, Side 1), 10 mA (Average Output Current per Pin, Side 2); the most conservative is kept",
          "source_page": 4,
          "source": "datasheet"
        }
      ]
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "π120e30"
  ],
  "discovery_pitch": "π120E30 (2Pai Semi) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "120e30.kicad_sym",
    "120e30.kicad_mod",
    "120e30.glb",
    "120e30.step",
    "120e30-etched.step",
    "120e30.lbr",
    "docs/hero.png",
    "docs/120e30-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "pads.json",
    "120e30-etched.glb",
    "120e30-hero.glb"
  ],
  "visibility": "public",
  "updated_at": "2026-09-24T14:25:47.505Z",
  "description": "2Pai Semi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-N. Datasheet-verified pinout, KiCad symbol/footprint/3D.",
  "org": "adom"
}