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Contents

README

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π110M30

2Pai Semi · Pre-ordered Products · SOIC-8

π110M30 from 2Pai Semi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply Voltage for Isolator Side 1, which must operate between 3.0 V and 5.5 V per the recommended operating conditions.
2 VIN power_in Logic Input for the channel, which must not exceed VDD1 + 0.5 V per the absolute maximum input voltage rating.
3 VDD1 power_in Supply Voltage for Isolator Side 1, which must operate between 3.0 V and 5.5 V per the recommended operating conditions.
4 GND1 power_in Ground 1, the ground reference for Isolator Side 1.
5 GND2 power_in Ground 2, the ground reference for Isolator Side 2.
6 VOUT output Logic Output for the channel; for the π110M30 variant the output defaults to Low when the input side is unpowered or the input is open.
7 GND2 power_in Ground 2, the ground reference for Isolator Side 2.
8 VDD2 power_in Supply Voltage for Isolator Side 2, which must operate between 3.0 V and 5.5 V per the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer 2Pai Semi
Package SOIC-8
Category Electronic Tools/Instruments/Consumables
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDDx 3 5.5 V 2
Supply Voltages (VDD1-GND1, VDD2-GND2) -0.5 7 V 2
Ambient Operating Temperature (TA) TA -40 125 °C 2
Ambient Operating Temperature (TA) Range TA -40 125 °C 2
Junction Temperature TJ -40 150 °C 2
Storage Temperature (TST) Range TST -65 150 °C 2
Common-Mode Transients Immunity -200 200 kV/µs 2
Average Output Current per Pin, Side 1 Output Current IO1 -10 10 mA 2
Average Output Current per Pin, Side 2 Output Current IO2 -10 10 mA 2
Data Rate 0 10 Mbps 2
Minimum Pulse Width PW 100 ns Within pulse width distortion (PWD) limit 3
Propagation Delay Time (5 V operation) tpHL, tpLH 5.5 8 12.5 ns @ 5VDC supply 3
Propagation Delay Time (3.3 V operation) tpHL, tpLH 6.5 9 13.5 ns @ 3.3VDC supply 3
Pulse Width Distortion (5 V) PWD 0 0.3 3 ns @ 5VDC supply; /tpHL - tpLH/ 3
Pulse Width Distortion (3.3 V) PWD 0 0.3 3 ns @ 3.3VDC supply; /tpHL - tpLH/ 3
Common-Mode Transient Immunity CMTI 75 kV/µs VIN = VDDx2 or 0V, VCM = 1000 V 3
ESD (HBM - Human body model) ESD -8 8 kV Human body model (HBM), ±8 kV as printed 3
VDDx1 Undervoltage Rising Threshold VDDxUV+ 2.45 2.75 2.95 V 4
VDDx1 Undervoltage Falling Threshold VDDxUV− 2.3 2.6 2.75 V 4
Input Current per Signal Channel IIN -10 0.5 10 µA 0 V ≤ Signal voltage ≤ VDDX1 4
Low Level Output Voltage (20 µA output current) VOL 0 0.1 V 20 µA output current 4
Low Level Output Voltage (2 mA output current) VOL 0.1 0.2 V 2 mA output current 4
Quiescent Supply Current IDD1 (5 VDC, VI=0V for π110M30) IDD1 (Q) 0.06 0.08 0.1 mA 5VDC supply, VI=0V, CL=0 pF, TA=25°C 4
Quiescent Supply Current IDD1 (5 VDC, VI=5V for π110M30) IDD1 (Q) 0.15 0.19 0.25 mA 5VDC supply, VI=5V, CL=0 pF, TA=25°C 4
Quiescent Supply Current IDD1 (3.3 VDC, VI=0V for π110M30) IDD1 (Q) 0.06 0.08 0.1 mA 3.3VDC supply, VI=0V, CL=0 pF, TA=25°C 4
Quiescent Supply Current IDD1 (3.3 VDC, VI=3.3V for π110M30) IDD1 (Q) 0.11 0.14 0.18 mA 3.3VDC supply, VI=3.3V, CL=0 pF, TA=25°C 4
Rated Dielectric Insulation Voltage 3000 V rms 1-minute duration 4
Minimum External Air Gap (Clearance) L (CLR) 4 mm Measured from input terminals to output terminals, shortest distance through air 4
Minimum External Tracking (Creepage) L (CRP) 4 mm Measured from input terminals to output terminals, shortest distance path along body 4
Minimum Internal Gap (Internal Clearance) 11 µm Insulation distance through insulation 4
Tracking Resistance (Comparative Tracking Index) CTI 400 V DIN EN 60112 (VDE 0303-11):2010-05, IEC 60112:2003 + A1:2009 4
Resistance (Input to Output) RIO 1011 Ω 5
Capacitance (Input to Output) CIO 0.6 pF @1MHz 5
Input Capacitance CI 3 pF @1MHz 5
IC Junction to Ambient Thermal Resistance θJA 100 °C/W Thermocouple located at center of package underside 5
Maximum Safety Temperature TS 150 °C Maximum value allowed in the event of a failure (see Figure 4) 6
Maximum Power Dissipation at 25°C PS 1.25 W Maximum value allowed in the event of a failure (see Figure 4) 6
Maximum repetitive peak isolation voltage VIORM 565 Vpeak DIN VDE V 0884-11 Basic insulation 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN V VDE V 0884-11, each π110M3x is proof tested by applying an insulation test voltage ≥ 848V peak for 1 sec (partial discharge detection limit = 5 pC). 5

CAD (KiCad official)

  • Symbol: π110M30
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: 110m30-etched.step / 110m30-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 110m30.step / 110m30.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 2Pai Semi datasheet (12 pp, sha256 d00e887193e90357, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF