board
Solar MPPT Power System
Public Unreviewedby TylerK
A 30 W solar battery charger with regulated 5 V and 3.3 V rails: an STM32G031 running perturb & observe MPPT and a CC/CV charge state machine, steering a TI LM5175 4-switch buck-boost through a single analog control input. Four-layer KiCad board, schematic and PCB generated from Python, with an electrothermal simulation run against the published board file.
← Commit history
add electrothermal simulation: peak 62.7 C board temperature (hotspot is the LM317, not the FETs) and worst-case VBATT copper path at 175.5 mOhm / 1.01 W
10 files changed
+582
README.md+32docs/sim-current-density.pngdocs/sim-thermal.pngdocs/simulation/05-electrothermal-simulation.md+81docs/simulation/current-density-maps.pngdocs/simulation/current-density-summary.csv+16docs/simulation/mesh-convergence.csv+4docs/simulation/simulation-results.json+445docs/simulation/thermal-map.pngdocs/simulation/thermal-sensitivity.csv+4README.md+32@@ -101,6 +101,34 @@ through-hole TO-220, chosen for easy heatsinking and hand assembly, and its 2.54 pitch puts a hard floor under how tight this loop can get. An all-SMD switch and Schottky would do better, and that would be a component respin, not a layout tweak. +## Electrothermal simulation++A DC current-density and steady-state thermal screening run was done on **this exact+board** — the simulation's recorded board SHA-256 matches the `.kicad_pcb` published here.++++A deliberately conservative composite case — every documented worst-case loss applied at+once, 6.34 W total — at 25 °C ambient with natural convection gives a **62.7 °C peak board+temperature** and a 30.3 °C area average. The hotspot, marked ✕ at (20.5, 69.5) mm, is+**U9, the LM317 linear regulator** — not either switching FET. That is worth holding against+the design record: the calculations doc justifies making the 3.3 V rail linear on the grounds+that 1.7 W is "modest and thermally manageable." Thermally it survives, but it does make the+most ordinary part on the board its hottest point. Q4 is second, at 54.9 °C near-source.++++The worst copper path is the battery bus feeding the 5 V stage: **175.5 mΩ, a 421 mV drop+and 1.01 W of copper loss at 2.4 A** — largely a consequence of how far VBATT has to travel+across a 242 mm board from J2 to the 5 V input. Ground returns, by contrast, are negligible+(0.53 mΩ across the plane at 3 A).++Both are **screening models, not sign-off**: board-surface temperature rather than junction+temperature, DC only — no switching, transient or EMI behaviour — and copper only, with+component, connector, fuse, shunt and solder-joint resistance excluded. Method, mesh+convergence and sensitivity data are in+[`docs/simulation/`](docs/simulation/05-electrothermal-simulation.md).+ ## Verified specifications Every number below was read back out of the source files or produced by KiCad 10.0.2,@@ -225,6 +253,9 @@ plus what the files show: - **Resolve the stackup/thickness question** (note 4 above) with your fab. - **Clear the 4 dangling tracks and tidy silkscreen** near the densest clusters — cosmetic, but worth a pass before ordering.+- **Check the LM317 (U9) first, not the FETs.** The thermal screening run puts the board's+ hotspot at the 3.3 V linear regulator, ahead of both switching stages. If the 3.3 V rail+ will actually run near 1 A, plan for heatsinking it or reconsider the linear choice. - **Thermals are calculated, not measured**: Q4 ≈ 1.4 W, Q1 ≈ 0.5 W. No dedicated thermal vias were added — a deliberate choice, since more copper at the switch node works against the EMI goal. If a prototype runs hot, the documented fix is a small copper@@ -234,6 +265,7 @@ plus what the files show: ``` docs/ the four design documents, plus the page images+docs/simulation/ electrothermal run: report, full figures, sensitivity data kicad/ mppt-power-system.kicad_sch / .kicad_pcb / .kicad_pro kicad/generator-scripts/ the Python that emits both files hardware/ STEP + GLB 3D models, schematic PDF, BOM CSV
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docs/simulation/05-electrothermal-simulation.mdadded+81@@ -0,0 +1,81 @@+# MPPT board electrothermal simulation++Run: 2026-09-16 +Board SHA-256: `5ca7bb1a4f28de16ff866d5f8a859c2b3b5ed3d0537ad618ee0666457358595b` +KiCad native validation: **0 errors, 0 unconnected items, 43 warnings** after zone refill (KiCad 10.0.2).++## Outcome++The saved board is electrically connected under KiCad's checked rules. In the geometry-derived DC model, the largest copper voltage drop is **421.245 mV** (battery_to_5V_2p4A), the highest effective copper resistance is **175.519 mΩ** (battery_to_5V_2p4A), and the largest copper loss is **1010.99 mW** (battery_to_5V_2p4A). These figures exclude component, connector, fuse, shunt, inductor, contact, and solder-joint resistance.++The conservative composite thermal case injects **6.340 W** into the board. At 25°C ambient with 10 W/m²K natural convection per side plus linearized solder-mask radiation, the collapsed board model predicts a **62.7°C** peak board temperature and **30.3°C** area average. This is a board-surface screening result, **not a semiconductor junction-temperature prediction**.++## DC current cases++| Case | Net | Load (A) | R (mΩ) | Drop (mV) | Copper loss (mW) | J p99 (A/mm²) |+|---|---|---:|---:|---:|---:|---:|+| panel_raw_5A | `/PANEL_P_RAW` | 5.00 | 9.961 | 49.806 | 249.03 | 170.91 |+| panel_fused_5A | `/PANEL_P_FUSED` | 5.00 | 1.286 | 6.432 | 32.16 | 89.28 |+| panel_protected_2p2A | `/PANEL_P_PROT` | 2.20 | 37.921 | 83.426 | 183.54 | 64.16 |+| charge_input_2p2A | `/VIN_CHG` | 2.20 | 11.565 | 25.443 | 55.98 | 78.39 |+| charge_switch_peak_2p26A | `/SW_CHG` | 2.26 | 17.492 | 39.533 | 89.34 | 64.06 |+| charge_to_battery_2A | `/VBATT` | 2.00 | 125.914 | 251.827 | 503.65 | 67.51 |+| battery_to_5V_2p4A | `/VBATT` | 2.40 | 175.519 | 421.245 | 1010.99 | 81.37 |+| five_volt_input_2p4A | `/VIN_5V` | 2.40 | 11.683 | 28.039 | 67.29 | 79.09 |+| five_volt_switch_peak_2p33A | `/SW_5V` | 2.33 | 17.526 | 40.835 | 95.15 | 67.40 |+| five_volt_rail_2A | `/V5V_RAIL` | 2.00 | 37.701 | 75.402 | 150.80 | 67.36 |+| five_volt_output_2A | `/V5V_OUT` | 2.00 | 108.997 | 217.993 | 435.99 | 67.34 |+| three_volt_three_rail_1A | `/V3V3_RAIL` | 1.00 | 18.547 | 18.547 | 18.55 | 33.74 |+| three_volt_three_output_1A | `/V3V3_OUT` | 1.00 | 95.129 | 95.129 | 95.13 | 33.68 |+| load_ground_return_3A | `GND` | 3.00 | 0.531 | 1.594 | 4.78 | 1.47 |+| charge_ground_return_2A | `GND` | 2.00 | 1.079 | 2.158 | 4.32 | 0.84 |++`j_max` is retained in the CSV/JSON but is contact- and mesh-sensitive; p99 is the more stable screening metric. All current plots show the maximum magnitude over the four copper layers. Floating copper components were omitted from the active solve rather than assigned invented current.++## Thermal sources and base-case board temperature++| Ref | Applied loss (W) | Average modeled board temperature near source (°C) |+|---|---:|---:|+| Q4 | 1.400 | 54.9 |+| Q1 | 0.500 | 40.7 |+| U9 | 1.700 | 60.7 |+| Q10 | 0.360 | 39.2 |+| D9 | 0.400 | 44.5 |+| D14 | 0.650 | 42.3 |+| RS1 | 0.242 | 44.3 |+| RS2 | 0.288 | 38.1 |+| L1 | 0.400 | 38.7 |+| L2 | 0.400 | 37.1 |++Q4 (1.4 W), Q1 (0.5 W), U9 (1.7 W), and D9 (0.4 W) come from the project calculations/review. Q10/D14 are first-order calculations from the documented 14.4 V, 2.3 A, 50 kHz stage. RS1/RS2 use the 2.2/2.4 A limit values. L1/L2 use the documented DCR upper bound of 0.1 Ω. Applying every worst-case loss simultaneously is conservative and not a single rigorously coherent operating point.++| Convection per side (W/m²K) | Peak board (°C) | Average board (°C) | Hotspot x,y (mm) |+|---:|---:|---:|---:|+| 5 | 68.8 | 32.6 | 20.5, 69.5 |+| 10 | 62.7 | 30.3 | 20.5, 69.5 |+| 20 | 56.5 | 28.3 | 20.5, 69.5 |++## Validation and sensitivity++- Current grid: 0.20 mm for power rails and 1.00 mm for the broad GND planes; selected cases repeated at 0.15/0.75 mm. Largest selected resistance change: **7.63%**.+- Known 50 mm × 2 mm × 35 µm copper strip: analytic **12.314 mΩ**, discretized **12.265 mΩ** (0.40% error).+- Copper modeled at 20°C. The CSV includes the uniform 80°C resistivity sensitivity (+23.6%).+- Via plating is provisional at 25 µm; 15/25/35 µm sensitivity is in `via-plating-sensitivity.csv`.+- Joule power balance and solver residuals are recorded per case. Thermal energy-balance error is recorded per convection case.++## Important limits++- Native KiCad copper, pads, vias, tracks, and refilled zones are used. Rasterization still approximates curved edges, thermal spokes, and contact current crowding.+- The DC solve is not a switching/transient, EMI, fuse, connector, or component-resistance model. It does not establish a current rating.+- The thermal solve collapses the four copper layers and FR-4 into a 2D sheet. It assumes all listed component loss enters the PCB, both board faces see the same ambient, no enclosure/contact heatsink exists, and solder-mask emissivity is 0.9. Package-to-air paths, junction-to-case resistance, lead conduction, airflow obstruction, cables, and thermal feedback are omitted.+- The project's Q4 1.4 W calculation combines 24 V with 5 A even though the same design notes describe a 30 W panel (1.25 A at 24 V). Treat it as a conservative stress assumption, not a coherent rated-panel operating point.+- KiCad reported 43 warnings, including dangling tracks, isolated GND copper, footprint-library mismatches, and silkscreen items. None were suppressed or edited for this run.++## Artifacts++- `current-density-maps.png` — all DC cases+- `thermal-map.png` — base thermal case and copper-layer coverage+- `current-density-summary.csv`, `thermal-sensitivity.csv` — compact results+- `current-fields.npz`, `thermal-field.npz` — numerical fields+- `simulation-results.json` — full assumptions, results, checks, and sensitivities+- `run_simulations.py`, `requirements.txt` — reproducibility
docs/simulation/current-density-maps.pngadded⋯ 1 unchanged line ⋯
docs/simulation/current-density-summary.csvadded+16@@ -0,0 +1,16 @@+name,net,pitch_mm,load_A,voltage_drop_mV,resistance_mOhm,copper_loss_mW,joule_balance_error_pct,normalized_residual,j_p95_A_per_mm2,j_p99_A_per_mm2,j_max_A_per_mm2,conductor_nodes,floating_components_omitted,plated_layer_links,resistance_at_80C_mOhm +panel_raw_5A,/PANEL_P_RAW,0.2,5.0,49.806208721938546,9.96124174438771,249.03104360969274,9.022223950547307e-11,4.726326823791048e-12,143.76631556116038,170.91132437584199,211.15154589726635,2114,0,9,12.310102547714331 +panel_fused_5A,/PANEL_P_FUSED,0.2,5.0,6.431680047645656,1.2863360095291312,32.158400238228275,1.8211187159539977e-11,5.7099768762663175e-12,59.38103510112449,89.2848325659366,119.04748840618393,2594,0,12,1.5896540405761004 +panel_protected_2p2A,/PANEL_P_PROT,0.2,2.2,83.42618054739508,37.92099115790685,183.53759720426916,1.1995664965081722e-09,5.7282212025037035e-12,48.68432475432521,64.15503690506287,90.13486867207136,14123,0,51,46.86276087294128 +charge_input_2p2A,/VIN_CHG,0.2,2.2,25.44346657104819,11.565212077749175,55.975626456306024,1.028891020047562e-11,1.3209109815980474e-11,69.72986118283451,78.38569501743824,93.30398993416779,4875,0,15,14.29228908568243 +charge_switch_peak_2p26A,/SW_CHG,0.2,2.26,39.53256398603792,17.492284949574305,89.34359460844567,4.221883776553807e-11,7.396891885847672e-12,59.22871376931571,64.06204228844506,93.13102954332481,2166,0,6,21.616965740683927 +charge_to_battery_2A,/VBATT,0.2,2.0,251.82738256042174,125.91369128021087,503.6547651208435,2.647624855802421e-10,1.8027602415535887e-10,67.34350299646638,67.50854686755962,86.28080704479328,13889,0,39,155.6041396840846 +battery_to_5V_2p4A,/VBATT,0.2,2.4,421.2453705495039,175.5189043956266,1010.988889318809,6.841289228677898e-10,1.6635953299620302e-10,80.81220358603494,81.37235734005412,105.55193788824985,13889,0,39,216.90626205211535 +five_volt_input_2p4A,/VIN_5V,0.2,2.4,28.03900088379791,11.682917034915796,67.29360212111499,2.2685019240196033e-13,1.1699043940578816e-11,57.142891297246315,79.09113108526554,101.78617083680614,7178,0,18,14.43774887174894 +five_volt_switch_peak_2p33A,/SW_5V,0.2,2.33,40.834908651104314,17.525711867426743,95.14533715707304,5.746838005578941e-12,7.827565770903356e-12,59.65262362108221,67.39543860505383,96.01561895400904,2066,0,6,21.65827472576597 +five_volt_rail_2A,/V5V_RAIL,0.2,2.0,75.40221542942827,37.701107714714134,150.8044308588566,3.5691001867314553e-10,4.505373557796644e-11,48.774230666165124,67.3563187866631,82.0472951930183,8990,0,15,46.59102891384373 +five_volt_output_2A,/V5V_OUT,0.2,2.0,217.99309427410296,108.99654713705148,435.98618854820603,1.0695147749869803e-11,4.472299569868434e-11,67.3416287306037,67.3445005922251,84.45464428412588,6246,0,6,134.69793295196823 +three_volt_three_rail_1A,/V3V3_RAIL,0.2,1.0,18.54730621894965,18.54730621894965,18.54730621894965,3.157561742801352e-11,1.914225181253202e-11,33.67175166863305,33.74162440735455,42.308266065745975,3352,0,12,22.920761025377978 +three_volt_three_output_1A,/V3V3_OUT,0.2,1.0,95.12935541736074,95.12935541736074,95.1293554173607,1.4639392860429606e-10,4.46310799767036e-11,33.67175148519661,33.67906790478265,41.143197220445884,7126,0,6,117.56085742477441 +load_ground_return_3A,GND,1.0,3.0,1.5937465297616618,0.5312488432538872,4.781239589284985,3.9910064909753884e-13,3.02661686969444e-11,0.5330545447585362,1.4670954572126862,5.633835561896317,68871,8,97,0.6565173204931538 +charge_ground_return_2A,GND,1.0,2.0,2.158209252682271,1.0791046263411355,4.316418505364542,3.8179506925239315e-13,3.444930652776806e-11,0.5321022729613987,0.8415340404335971,4.439289169924557,68871,8,97,1.3335574972323752
docs/simulation/mesh-convergence.csvadded+4@@ -0,0 +1,4 @@+name,coarse_pitch_mm,fine_pitch_mm,coarse_resistance_mOhm,fine_resistance_mOhm,difference_pct +panel_raw_5A,0.2,0.15,9.96124174438771,9.726385789345526,2.4146271814495517 +five_volt_switch_peak_2p33A,0.2,0.15,17.525711867426743,17.401773756183893,0.7122153924039366 +load_ground_return_3A,1.0,0.75,0.5312488432538872,0.5751404297562166,7.631455594407369
docs/simulation/simulation-results.jsonadded+445@@ -0,0 +1,445 @@+{+ "board": "/mnt/c/Users/kirkt/Documents/mppt-power-system-test/mppt-power-system.kicad_pcb",+ "board_sha256": "5ca7bb1a4f28de16ff866d5f8a859c2b3b5ed3d0537ad618ee0666457358595b",+ "model": {+ "current_grid_mm": 0.2,+ "fine_grid_mm": 0.15,+ "ground_grid_mm": 1.0,+ "ground_fine_grid_mm": 0.75,+ "thermal_grid_mm": 1.0,+ "copper_resistivity_20C_ohm_m": 1.724e-08,+ "copper_tempco_per_C": 0.00393,+ "via_plating_assumption_um": 25.0,+ "ambient_C": 25.0+ },+ "native_drc": {+ "kicad_version": "10.0.2",+ "errors": 0,+ "unconnected": 0,+ "warnings": 43,+ "note": "Run through Adom Bridge with zone refill on 2026-09-16."+ },+ "current_cases": [+ {+ "name": "panel_raw_5A",+ "net": "/PANEL_P_RAW",+ "pitch_mm": 0.2,+ "load_A": 5.0,+ "voltage_drop_mV": 49.806208721938546,+ "resistance_mOhm": 9.96124174438771,+ "copper_loss_mW": 249.03104360969274,+ "joule_balance_error_pct": 9.022223950547307e-11,+ "normalized_residual": 4.726326823791048e-12,+ "j_p95_A_per_mm2": 143.76631556116038,+ "j_p99_A_per_mm2": 170.91132437584199,+ "j_max_A_per_mm2": 211.15154589726635,+ "conductor_nodes": 2114,+ "floating_components_omitted": 0,+ "plated_layer_links": 9,+ "resistance_at_80C_mOhm": 12.310102547714331+ },+ {+ "name": "panel_fused_5A",+ "net": "/PANEL_P_FUSED",+ "pitch_mm": 0.2,+ "load_A": 5.0,+ "voltage_drop_mV": 6.431680047645656,+ "resistance_mOhm": 1.2863360095291312,+ "copper_loss_mW": 32.158400238228275,+ "joule_balance_error_pct": 1.8211187159539977e-11,+ "normalized_residual": 5.7099768762663175e-12,+ "j_p95_A_per_mm2": 59.38103510112449,+ "j_p99_A_per_mm2": 89.2848325659366,+ "j_max_A_per_mm2": 119.04748840618393,+ "conductor_nodes": 2594,+ "floating_components_omitted": 0,+ "plated_layer_links": 12,+ "resistance_at_80C_mOhm": 1.5896540405761004+ },+ {+ "name": "panel_protected_2p2A",+ "net": "/PANEL_P_PROT",+ "pitch_mm": 0.2,+ "load_A": 2.2,+ "voltage_drop_mV": 83.42618054739508,+ "resistance_mOhm": 37.92099115790685,+ "copper_loss_mW": 183.53759720426916,+ "joule_balance_error_pct": 1.1995664965081722e-09,+ "normalized_residual": 5.7282212025037035e-12,+ "j_p95_A_per_mm2": 48.68432475432521,+ "j_p99_A_per_mm2": 64.15503690506287,+ "j_max_A_per_mm2": 90.13486867207136,+ "conductor_nodes": 14123,+ "floating_components_omitted": 0,+ "plated_layer_links": 51,+ "resistance_at_80C_mOhm": 46.86276087294128+ },+ {+ "name": "charge_input_2p2A",+ "net": "/VIN_CHG",+ "pitch_mm": 0.2,+ "load_A": 2.2,+ "voltage_drop_mV": 25.44346657104819,+ "resistance_mOhm": 11.565212077749175,+ "copper_loss_mW": 55.975626456306024,+ "joule_balance_error_pct": 1.028891020047562e-11,+ "normalized_residual": 1.3209109815980474e-11,+ "j_p95_A_per_mm2": 69.72986118283451,+ "j_p99_A_per_mm2": 78.38569501743824,+ "j_max_A_per_mm2": 93.30398993416779,+ "conductor_nodes": 4875,+ "floating_components_omitted": 0,+ "plated_layer_links": 15,+ "resistance_at_80C_mOhm": 14.29228908568243+ },+ {+ "name": "charge_switch_peak_2p26A",+ "net": "/SW_CHG",+ "pitch_mm": 0.2,+ "load_A": 2.26,+ "voltage_drop_mV": 39.53256398603792,+ "resistance_mOhm": 17.492284949574305,+ "copper_loss_mW": 89.34359460844567,+ "joule_balance_error_pct": 4.221883776553807e-11,+ "normalized_residual": 7.396891885847672e-12,+ "j_p95_A_per_mm2": 59.22871376931571,+ "j_p99_A_per_mm2": 64.06204228844506,+ "j_max_A_per_mm2": 93.13102954332481,+ "conductor_nodes": 2166,+ "floating_components_omitted": 0,+ "plated_layer_links": 6,+ "resistance_at_80C_mOhm": 21.616965740683927+ },+ {+ "name": "charge_to_battery_2A",+ "net": "/VBATT",+ "pitch_mm": 0.2,+ "load_A": 2.0,+ "voltage_drop_mV": 251.82738256042174,+ "resistance_mOhm": 125.91369128021087,+ "copper_loss_mW": 503.6547651208435,+ "joule_balance_error_pct": 2.647624855802421e-10,+ "normalized_residual": 1.8027602415535887e-10,+ "j_p95_A_per_mm2": 67.34350299646638,+ "j_p99_A_per_mm2": 67.50854686755962,+ "j_max_A_per_mm2": 86.28080704479328,+ "conductor_nodes": 13889,+ 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docs/simulation/thermal-map.pngadded⋯ 1 unchanged line ⋯
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