Solar MPPT Power System

@@ -0,0 +1,376 @@+# Solar MPPT Power System — Architecture Analysis++**Status:** Pre-schematic analysis. No components placed, no KiCad files created yet.+**Scope note:** Per instruction, this design assumes **no battery / no energy-storage+element** anywhere in the power path, even though the final product will include one.+Every decision below is made as if the regulated 5 V/3.3 V rails are the only "sink"+the panel ever sees. Section 8 flags exactly what changes once a battery is added later,+so that decision isn't accidentally foreclosed by this phase's choices.++---++## 1. Is "Solar → MPPT → regulated bus/buck-boost → 5 V + 3.3 V" electrically sensible?++Yes, with one important caveat about what "MPPT" actually *means* here.++The topology itself — a wide-range front-end pulling power from a source with a+nonlinear I-V curve, converting to a stiff intermediate bus, then independent+point-of-load (POL) regulators for each output — is standard and sound. The caveat is+that **classic MPPT and battery-less output regulation are two different control+objectives that will fight each other unless one is explicitly subordinate to the+other.** Section 2 explains why, and the architecture in Section 4 is built specifically+to resolve that conflict rather than ignore it.++A second sanity check worth doing up front is the power budget:++- Combined max simultaneous load: 5 V × 2 A + 3.3 V × 1 A = 10 W + 3.3 W = **13.3 W**+- Panel rated max power: **~30 W**++The panel is sized at roughly **2.25× the maximum simultaneous load**. That is not+over-engineering for no reason — it's exactly what a battery-less design needs, because+the full 13.3 W load must be satisfiable even when the panel is delivering well under+its rated power (partial cloud, low sun angle, dust, non-ideal orientation, elevated+cell temperature). Section 3 quantifies how far irradiance can drop before the load can+no longer be fully served.++---++## 2. How MPPT works with no battery++In a conventional MPPT **charge controller**, the battery is a forgiving, nearly+voltage-fixed sink: the controller is free to pull the panel to whatever current+corresponds to its true maximum power point (Vmp, Imp), because the battery will accept+whatever power arrives (up to its own charge-current limit). The battery is the buffer+that absorbs the mismatch between "power available" and "power currently wanted."++**Without a battery, there is no buffer.** The only sink is the load itself, and the+load wants a *specific, fixed voltage* (5 V, 3.3 V), not "whatever power is available."+That creates a direct conflict if both the MPPT stage and the output stage each try to+run their own voltage-regulation loop: one loop wants to hold the *input* at Vmp, the+other wants to hold the *output* at 5 V/3.3 V, and if load demand and available panel+power don't match at that exact instant, the two loops disagree about what the+converter's duty cycle should be. Two independent voltage loops stacked on the same+power stage is a classic recipe for instability (fighting loops, limit-cycling, or+one loop simply overriding the other unpredictably).++**The resolution — and the actual behavior this design implements — is to make the two+loops operate in mutually exclusive regions, not simultaneously:**++- **When available panel power ≥ load demand** (the common case in good sun): the+  output-voltage loop is authoritative. The pre-regulator draws only as much current as+  the load needs to hold 5 V/3.3 V in regulation. Because the load is drawing *less*+  current than Impp, the panel's own I-V curve pushes its terminal voltage *up*, past+  Vmp, toward Voc. **True MPPT tracking is not engaged in this regime — and that's+  correct, not a bug.** There is no benefit to extracting more power than the load can+  use with nowhere to put it; the "extra" capability just shows up as the panel sitting+  at a higher, lighter-loaded voltage than its MPP.++- **When available panel power < load demand** (low sun, cloud, high panel temp): the+  output loop *cannot* be satisfied — there simply isn't enough power. If nothing+  intervened, the output regulator would keep increasing duty cycle trying to pull more+  input current, which (per the solar cell I-V curve) collapses panel voltage rapidly+  past MPP toward Isc/near-zero. **This is where the MPPT loop takes over as an input+  voltage floor**: it monitors panel voltage and, the instant panel voltage tries to sag+  below the tracked Vmp setpoint, it overrides the output loop and folds back output+  current until panel voltage stabilizes at Vmp. In this regime the pre-regulator is, in+  effect, a constant-input-voltage (constant-power) source, and downstream output+  voltage is whatever that limited power can sustain (see Section 3).++So concretely: **MPPT in this design is not a mode that's "always tracking the peak of+the P-V curve." It is a current-foldback floor that only becomes active exactly when+the load asks for more than the panel can currently give — which is precisely the+situation a battery-less system needs it for.** This is a well-established technique+(often called input-voltage regulation, VINDPM, or constant-voltage-input regulation in+IC datasheets) and is exactly how solar-fed regulators without storage are built in+practice.++---++## 3. What happens when available solar power is less than the load requires++This is the physical limit of a battery-less design, and no amount of clever control+loop design changes the underlying fact: **if there is nowhere to store energy, the+system cannot deliver more instantaneous power than the panel is currently producing.**+The goal isn't to prevent this — it's impossible to prevent — the goal is to make the+*response* to it clean, predictable, and non-destructive.++**Quantifying the threshold.** Assuming realistic conversion efficiencies (pre-regulator+~93%, each POL buck ~90%, both independently fed from the intermediate bus):++```+Required panel power  =  13.3 W  ÷  0.93 (stage 1)  ÷  0.90 (stage 2)+                      ≈  15.9 W+```++Against a 30 W-rated panel, **that's ~53% of rated power** — meaning, roughly, the+system can serve the *full* simultaneous 2 A + 1 A load down to about half of rated+full-sun irradiance. Below that threshold, the panel physically cannot supply both+rails at full current simultaneously, and something must give.++**The designed-for sequence of events as available power drops further:**++1. MPPT foldback (Section 2) holds panel voltage at Vmp and reduces the current handed+   to the intermediate bus. The bus voltage droops below its nominal ~9 V target.+2. The two POL regulators keep 5 V/3.3 V in tight, clean regulation as long as the bus+   stays above their dropout requirement (this is *why* the bus is targeted well above+   5 V — see Section 4 — it buys headroom before the outputs themselves are affected).+3. Once available power drops far enough that the bus sags below POL dropout, output+   regulation is lost. **At this point brownout is correct, physically-unavoidable+   behavior, not a fault to be engineered around.** What *is* an engineering+   responsibility is making sure that transition is graceful:+   - A defined UVLO threshold with hysteresis on the intermediate bus (and/or on panel+     voltage) so the converter shuts down cleanly rather than limping in a+     partially-regulated, potentially damaging state.+   - Enough hysteresis that the system doesn't chatter (restart → immediately brown out+     → restart → …) at the threshold, which stresses components and can produce+     audible/EMI artifacts.+   - A soft-start on recovery so that when power returns, the outputs ramp up rather+     than slamming a discharged bus capacitance with full duty cycle.++**What this design deliberately does *not* attempt**, per your instruction: use a+battery, supercapacitor, or any other storage element to ride through this condition.+The consequence — accepted as correct for this phase — is that momentary cloud transients+under marginal irradiance will visibly brown out the outputs. If the final product's+battery is added at the intermediate bus (see Section 8), that's exactly the problem it+will solve; this board's job is to fail safely and recover cleanly without one.++---++## 4. Proposed power architecture++```+ Panel (6–24V, ≤30W)+      │+      ▼+ [Fuse] → [Reverse-Polarity Protection] → [OVP/TVS clamp] → [Input bulk + HF caps]+      │+      ▼+ STAGE 1 — MPPT Pre-Regulator+ 4-switch synchronous buck-boost, average-current-mode controller+ + MCU running P&O MPPT (reads Vin, Iin via ADC; sets operating point)+ + input-voltage foldback floor (Section 2/3)+      │+      ▼+ Intermediate DC bus, target ~9 V (semi-regulated: authoritative loop+ switches between "hold 9V" under light load and "hold Vmp, let bus droop"+ under power-limited conditions)+      │+      ├──────────────────────────────┐+      ▼                              ▼+ STAGE 2a — 5V Buck (2A)      STAGE 2b — 3.3V Buck (1A)+ independent POL regulator     independent POL regulator+ with own input UVLO           with own input UVLO+      │                              │+      ▼                              ▼+   5V rail                       3.3V rail+```++**Why an intermediate bus above 5 V, rather than regulating straight to 5 V in stage 1:**++- Vmp can legitimately sit *below* a naive 5 V target under real conditions — Vmp+  drops with rising cell temperature (a hot panel can lose meaningfully more than 10%+  of its 25°C-rated Vmp) — so a bus target with only ~1 V of margin above the stated 6 V+  input floor leaves no room for that. A 4-switch buck-boost stage 1 handles input above+  *or below* the bus target without drama, and a **~9 V bus** gives the downstream 5 V+  buck comfortable dropout margin even if Vin sags toward or below 6 V.+- Feeding both POL regulators from the *same* bus in parallel (rather than cascading+  3.3 V from the 5 V rail) avoids stacking conduction losses and lets each rail's+  transient response be independent of the other's load steps — relevant here because+  there's no battery to absorb cross-rail interaction.++**Why the two output regulators must NOT also try to be "smart" about the input:**+only **one** stage should own the MPPT/input-voltage decision. Stage 1 is the sole place+that decision is made; stage 2 regulators are simple, well-behaved, fixed-output bucks+whose only job is clean output regulation within their input operating range. Stacking+another adaptive loop downstream would reintroduce the multi-loop conflict from Section 2.++---++## 5. Candidate ICs and justification++### Stage 1 — MPPT pre-regulator: **TI LM5175 / LM5176** (4-switch synchronous buck-boost controller)++- **Input range:** rated to 60 V absolute — comfortably covers 6–24 V operating plus+  realistic Voc margin (see Section 6 risk on Voc) with no need to run near the part's+  ceiling.+- **Topology fit:** true 4-switch buck-boost — required because Vin (6–24 V) straddles+  the intended ~9 V bus in both directions.+- **Control fit:** average-current-mode control with an externally accessible+  feedback/compensation node. This is exactly what's needed to implement the+  input-voltage-foldback behavior from Section 2/3 — well-documented technique, used in+  published TI reference designs for solar-fed buck-boost front ends.+- **Controller vs. fully-integrated part:** a controller (external FETs) is chosen+  deliberately over an integrated buck-boost converter, because integrated parts rarely+  expose the current-sense and FB access needed to inject an MPPT loop; this is the same+  reason dedicated solar-charge-controller ICs are usually built the same way.+- **External MOSFETs:** sized for the worst-case continuous current (~5 A at Vin = 6 V,+  Section 6) with margin, voltage-rated with real headroom above worst-case Voc — exact+  part selection deferred to the schematic phase pending the specific panel's Voc spec.++*Lower-power alternative considered and rejected:* dedicated PV-MPPT ICs like STMicro+**SPV1040** implement fractional-Voc/P&O MPPT on-chip, but SPV1040 is **boost-only**+(output must exceed input) and its internal switch current rating targets single-cell/+low-power harvesting, not a clean fit for 30 W across a 6–24 V range needing both+step-up and step-down. Noted as a candidate only if a future revision drops to a+narrower, boost-only input range.++### MPPT control: small MCU running Perturb & Observe (or Incremental Conductance)++- Reads Vin (resistor divider) and Iin (amplified shunt, see below) via ADC, runs the+  MPPT algorithm in firmware, and sets the LM5175's operating point (PWM output + RC+  filter synthesizing an analog reference into the foldback comparator, or directly into+  the FB summing node).+- An MCU-based loop is chosen over a pure analog (op-amp) foldback circuit because it+  enables genuine adaptive P&O/IncCond tracking rather than a fixed fractional-Voc+  approximation, and it is how the large majority of real, mid-power (tens of watts)+  MPPT designs are actually built in production — satisfying the "practical to+  manufacture, not conceptual" requirement more directly than a discrete analog kludge.+- **Representative part:** any small Cortex-M0+/M0-class MCU with a timer/PWM and+  ≥2 ADC channels (e.g., ST **STM32G0** series, or equivalent from any established+  vendor) — cheap, extremely common, no exotic requirement. Exact part deferred; this+  is a "pick what's in stock" decision, not a critical-path one.+- **Current-sense IC:** TI **INA180**-class fixed-gain shunt monitor for Iin, rather+  than a raw shunt into the ADC directly — needed because a single shunt value has to+  serve both low-light (small signal, needs gain for resolution) and full-power (5 A,+  needs a small enough shunt to keep I²R loss low) conditions; an amplified current-sense+  IC resolves that tension far better than sizing the ADC's own reference/gain around a+  bare resistor.++### Stage 2a — 5 V / 2 A: **TI TPS562201** (or TPS562208) synchronous buck++- Integrated FET synchronous buck, input range comfortably covers the ~9 V bus,+  2–3 A class parts are a direct match for the 2 A requirement with margin, single-IC+  solution (simple BOM, easy to manufacture), widely stocked.++### Stage 2b — 3.3 V / 1 A: **TI TLV62569** synchronous buck (or same family as 5 V rail)++- Same reasoning as above at the smaller current point. **Recommendation:** where+  possible, prefer a part from the *same IC family* as the 5 V rail (just a smaller+  current-rated sibling, or the same part with different resistor-divider feedback+  values) to reduce distinct line items in the BOM — a genuine manufacturability win at+  negligible engineering cost.++### Protection++- **Reverse polarity:** an **active** P-channel (or N-channel + charge pump) "ideal+  diode" MOSFET stage, not a passive series diode. At the worst-case 5 A input current,+  a simple Schottky's ~0.4–0.5 V drop would waste ~2–2.5 W — a meaningful fraction of+  the ~15.9 W the system needs to serve full load near the brownout threshold from+  Section 3. That efficiency cost is unacceptable in a power-constrained solar design,+  so active protection is the right call despite the added parts count.+- **Overvoltage/transient protection:** TVS diode across the input, rated with real+  margin above worst-case Voc (see Section 6 risk — needs the actual panel's Voc spec+  to finalize the voltage rating), plus the fuse for sustained overcurrent fault+  conditions.+- **Fusing:** sized off the worst-case continuous input current (Section 6), not the+  nominal operating current — fast-blow fuse or resettable PTC, exact part chosen at+  schematic time once inrush behavior from the input bulk capacitance is known (PTC/fuse+  I²t rating must clear the capacitor charging inrush without nuisance-tripping).++---++## 6. Power/current calculations and major engineering risks++### Calculations++| Quantity | Value | Basis |+|---|---|---|+| Max simultaneous load power | 13.3 W | 5V×2A + 3.3V×1A |+| Assumed stage 1 efficiency | ~93% | typical for a well-designed synchronous 4-switch buck-boost at this power level |+| Assumed stage 2 efficiency (each) | ~90% | typical synchronous buck at these currents |+| Required panel power for full load | **~15.9 W** | 13.3 ÷ 0.93 ÷ 0.90 |+| Fraction of rated 30W panel needed | **~53%** | full-load-serviceable down to roughly half of rated irradiance |+| Worst-case continuous input current | **5.0 A** | 30W ÷ 6V (minimum input voltage) |+| Input current at max voltage | 1.25 A | 30W ÷ 24V |++*All efficiency figures are engineering estimates for architecture planning; they must+be re-derived from actual component loss data once parts are finalized.*++### Major engineering risks (in rough priority order)++1. **Voltage collapse / brownout under overload is physically unavoidable without+   storage** (Section 3). The risk isn't that it happens — it will — the risk is in the+   UVLO/hysteresis/soft-restart design not being clean, leading to chattering restarts+   that stress components or produce a noisy, unreliable-feeling product.+2. **Open-circuit voltage (Voc) exceeding the stated 24 V "operating max."** Voc is+   typically well above Vmp (often 20–30%+ higher) and rises further in cold weather.+   Every input-referred component (FETs, TVS, fuse, connector, input caps) must be rated+   against the real worst-case Voc of the *specific* panel to be used, not the 24 V+   figure — **this needs the actual panel datasheet before component ratings are+   finalized.**+3. **Reverse-polarity protection choice directly trades off against efficiency**, which+   is unusually tight in this design given the panel is oversized only ~2.25× the load+   (Section 1) specifically to cover partial-sun operation. An active ideal-diode circuit+   is recommended over a passive diode for exactly this reason (Section 5).+4. **Two-loop interaction / stability between stage 1's foldback and stage 2's+   independent regulation.** The architecture is designed so only one loop is+   authoritative at a time, but the transition between "voltage-mode" and+   "foldback-mode" at stage 1, and the transient response of stage 2 during a bus sag,+   both need real loop-compensation design and bench verification — this is not+   something to trust to simulation alone.+5. **Thermal design at the worst-case operating point** (Vin = 6 V, 5 A) — conduction+   losses are highest exactly where voltage margin is lowest. A solar product may also+   sit in an enclosure under direct sun with limited airflow, compounding this.+6. **MPPT algorithm assumes a single, unshaded panel/module.** Simple P&O can get stuck+   at a local maximum if the source P-V curve has multiple peaks (partial shading across+   a series-connected array). **Open question to confirm:** is the intended source a+   single panel/module, or a multi-panel array where partial shading is realistic? This+   materially affects whether basic P&O is sufficient or a more robust MPPT algorithm+   (or panel-level bypass diodes) is needed.+7. **No storage means no hold-up energy for load transients.** Fast load steps (e.g.,+   the 3.3 V rail suddenly pulling its full 1 A) must be absorbed entirely by output+   capacitance and stage 2's transient response — this raises the bar on output+   capacitor sizing and loop bandwidth compared to a battery-buffered design, and needs+   real transient-response validation at the schematic/prototype stage.++---++## 7. Requirements checklist (for cross-reference against later schematic work)++- [x] Architecture sensibility analyzed (Section 1)+- [x] MPPT-without-battery mechanism explained (Section 2)+- [x] Under-power behavior explained (Section 3)+- [x] Power architecture proposed (Section 4)+- [x] Candidate ICs selected + justified (Section 5)+- [x] Power/current calculations + risks (Section 6)+- [ ] Reverse-polarity protection — architecture decided (active ideal diode), part TBD+- [ ] Input overvoltage protection — architecture decided (TVS + fuse), rating pending panel Voc spec+- [ ] Fusing/current protection — target current known (~5A worst case), part TBD+- [ ] Input/output bulk + HF decoupling — placement decided (Section 4), values TBD at schematic phase+- [ ] Voltage/current sensing for MPPT — architecture decided (Section 5), exact shunt/divider values TBD+- [ ] Test points — not yet defined (schematic phase)++---++## 8. What changes when the battery is added later (not part of this design phase)++Flagged for awareness only, per your instruction to design this phase with no storage+in mind:++- The most natural integration point is **at the intermediate ~9 V bus**, between stage+  1 and stage 2 — that's already the place in this architecture where "available power+  vs. demanded power" is reconciled.+- Once a battery exists there, stage 1's role changes from "input-voltage-foldback+  pre-regulator" to a more conventional **MPPT battery charger**, and the two POL+  regulators would draw from the battery-buffered bus instead of the raw, foldback-prone+  stage-1 output — which removes essentially all of Section 3's brownout concern.+- None of the stage 1 IC choice, MPPT approach, or bus voltage target need to change to+  accommodate that later — they were chosen to already be compatible with a battery+  appearing at that node, even though none is assumed here.++---++## Open questions before proceeding to schematic++1. Is the "solar panel" a single module, or a multi-panel array (partial-shading risk,+   Section 6 #6)?+2. Do you have the actual candidate panel's datasheet (specifically Voc, and Vmp vs.+   temperature) so input protection ratings can be finalized rather than estimated?+3. Confirm the ~9 V intermediate bus target is acceptable, or state a preference.+4. Confirm the MCU-based MPPT approach (vs. a simpler fixed fractional-Voc analog+   approach with less design/firmware effort but no true peak tracking).++**Nothing has been placed in KiCad. This document is the complete pre-schematic+deliverable requested.** Let me know how you'd like to proceed — I can move to+block-level schematic capture once the open questions above are resolved (or you tell+me to proceed with the stated assumptions).

@@ -0,0 +1,338 @@+# Solar MPPT Charge System — Detailed Design Calculations (Rev 2, with battery)++## Revision context — what changed from Rev 1++- **Battery added**: 12 V nominal, assumed **sealed lead-acid (SLA/AGM)** (most common+  meaning of "a battery with 12V output"; a 4S LiFePO4 pack at ~12.8V nominal would use+  nearly identical charge-voltage numbers, so this design is not sensitive to that+  assumption — flagged for confirmation).+- **No MCU. "Basic components, no separate chips."** Interpreted as: no dedicated+  MPPT/buck-boost-controller/current-sense ICs. Building blocks used instead are the+  most generic, decades-old, multi-sourced parts available: op-amps (LM324), a+  comparator (LM393), a shunt reference (TL431), a timer (NE555), a zener reference,+  discrete BJTs and power MOSFETs, Schottky diodes. These are treated as "basic+  components," not as the specialty chips being avoided — please correct me if that+  reading is wrong.+- **Single panel confirmed** — simple P&O-style multi-peak shading risk from Rev 1 no+  longer applies.+- **Topology simplified from buck-boost to buck-only for the charge stage.** With the+  battery buffering the bus, the charge stage's only job is panel→battery, and charging+  a ~14.2V target requires Vin > ~15-16V regardless of topology. A buck-boost bought+  nothing extra here but added a second half-bridge and control complexity a basic-parts+  design doesn't need. Documented explicitly in Block 3 below, including what happens+  when Vin is below the buck's useful range (this is not a topology gap — it is+  standard, expected solar-charge-controller behavior).+- **3.3V now cascaded from 5V**, using a simple linear regulator — justified in Block 5.++---++## Block-by-block design++### Block 1 — Solar input & protection++**Fuse.** Sized off worst-case continuous input current across the full stated+survivability range (6–24V), not the realistic charging range: `30W / 6V = 5.0A`.+Target: **6.3A fast-blow fuse** (or resettable PTC rated ~6A hold / ~12A trip),+giving margin above the 5.0A worst case without excessive nuisance-trip risk.++**Reverse-polarity protection.** Self-biased P-channel MOSFET (no controller IC): the+FET's source ties to panel+, drain feeds the rest of the circuit; a gate pull-down+resistor to panel– turns it on in normal polarity (low Rds(on), low loss); reversed+input reverses the gate-source relationship and keeps it off. A small gate zener+(~15V) clamps gate-source voltage against Voc-driven overstress.+- **Verify:** at 5.0A worst case, Rds(on) must be low enough to keep conduction loss+  small. A common part like an **IRF4905** (55V, Rds(on) ≈ 0.02Ω) dissipates+  `I²R = 5² × 0.02 = 0.5W` — acceptable. Voltage rating needs margin over worst-case+  Voc (see Block 1 OVP below); 55V comfortably clears an assumed ~30V worst-case Voc.++**Overvoltage/transient protection.** TVS diode across the input, after the fuse and+reverse-protection FET. **Open item requiring the actual panel datasheet**: Voc is+typically 20–30%+ above Vmp and rises further in cold weather, so the true worst case+is unknown without the panel's real spec. Placeholder design assumption: worst-case+Voc ≈ 30V. TVS selected with standoff voltage above that (e.g., a 33V-clamp automotive-+grade TVS), leaving headroom below the 55V FET rating.++**Input bulk/HF capacitance.** Sized against the charge-stage buck's pulsed input+current (Block 3): RMS ripple current up to ~0.98A at the worst-case duty cycle+(Vin=24V). Specify **2× 100µF low-ESR electrolytic** (aggregate ripple-current rating+≥1A) **+ 1× 1µF ceramic** for high-frequency decoupling right at the switch node.++### Block 2 — MPPT sensing/control (charge-stage control loop, built from basic parts)++**Housekeeping bias supply (self-start requirement).** The charge-stage's control+circuitry (op-amps, comparator, timer) must be able to start switching from a fully+depleted battery, as long as the panel is illuminated — so it **cannot** be powered+from the battery/output side (that would be a startup deadlock). Instead: a simple+zener-based linear pre-regulator off the raw panel input (post-protection), independent+of battery state.+- Zener: **1N4740A (10V, 1W)** through a series resistor from panel+ (worst case up to+  ~30V assumed Voc) to the bias rail. Series resistor sized for a target zener current+  of ~10-15mA at minimum operating panel voltage (~16V, below which charging doesn't+  occur anyway): `R = (16V − 10V) / 12mA ≈ 500Ω` → **510Ω, rated for worst-case power at+  Voc=30V**: `(30−10)²/510 ≈ 7.8W` — this is a real, non-trivial dissipation at true+  open-circuit (no-load) panel voltage, and needs a real power resistor (rated ≥10W)+  or a small pre-regulator ahead of the zener to avoid wasting significant power under+  light-load/no-charging conditions. **Flagged as a refinement to revisit**: a simple+  two-resistor pre-divider or a small series NPN pass transistor (emitter-follower off+  the zener, so the zener only supplies base current, not the full bias-rail current)+  reduces this dissipation by roughly the transistor's current gain (hFE) and is the+  better production choice — noted here, will be implemented in the schematic as an+  NPN emitter-follower zener regulator (2N2222 or similar general-purpose NPN + the+  1N4740A zener on its base) rather than a bare zener, keeping series-resistor power+  low (a few mA of base current instead of the full ~12mA bias-rail current at Voc).++**Voltage-mode reference — 5.1V zener.** A **1N5231B (5.1V, 500mW)** off the bias rail+provides a stable, low-current reference for the Vin-sense and current-limit+comparisons (kept separate from the TL431 used in the output-voltage loop, so the+output loop's precision reference isn't loaded by the auxiliary comparisons).+Bias resistor from the ~10V housekeeping rail: target ~5mA through the zener,+`R = (10−5.1)/5mA ≈ 980Ω` → **1kΩ**.++**Panel-voltage (Vmp) sense divider.** Target Vmp ≈ 18V (typical Vmp for this class of+~30W nominal-12V-system panel; **adjustable** — retune once the actual panel's real+Vmp is known). Scaled against the 5.1V zener reference:+```+R_top = R_bottom × (Vmp / Vref − 1) = 10k × (18/5.1 − 1) ≈ 25.3k → use 25.5kΩ (E96)+```+Actual trip point with 25.5k/10k: **18.10V** (verified by calculation, not assumed).++**Input current sense.** Shunt **R_sense = 0.05Ω (1W)** in the panel input path.+At the worst-case 5.0A: `I²R = 5² × 0.05 = 1.25W` — fits a 1W part with modest margin;+a 2W part is recommended for safety margin. Signal at 5A = 0.25V; at the intended+current-limit trip (2.2A, chosen with ~15% headroom over the ~1.9A expected max+charging current) the shunt signal is only 0.11V — amplified ×20 by an LM324+difference amplifier (`Rf/Rin = 20`, e.g. Rin=1k, Rf=20k) to 2.2V for comparison+against the zener-derived reference.+```+Current-limit reference divider: R_top = 10k × (5.1/2.2 − 1) ≈ 13.2k → use 13.3kΩ (E96)+Verified trip: back-calculated to ≈2.19A+```++**Vmp error amplifier and current-limit comparator** — two sections of one LM324+quad op-amp package (third section reserved for the output-voltage-loop's role,+see below; fourth section available for monitoring buffering, Block 7).++**Output (battery) voltage loop — TL431 used directly as reference + error amp.**+Rather than a separate op-amp, the TL431's own 2.5V internal reference does double+duty: it compares the battery-voltage divider directly, and its cathode signal (through+its own bias resistor) becomes the error voltage. This is a standard, very+component-efficient technique.+```+Target Vbatt (single-stage CV, no temperature compensation in this basic-parts design):+14.2V — a deliberately conservative choice for a simple analog charger without+temp-comp (typical SLA absorption is 14.4-14.6V; 14.2V trades a little charge+completeness for safety margin against overcharge in a fixed-setpoint design).++R1 (top) = R2 × (Vbatt/Vref − 1) = 10k × (14.2/2.5 − 1) = 46.8k → use 46.4kΩ (E96)+Actual trip with 46.4k/10k: 14.10V (verified)+```+TL431 cathode bias resistor, fed from the housekeeping bias rail (~10V, available even+with a dead battery): `R = (10−2.5)/5mA = 1.5kΩ`.++**Combining the three loops (diode-OR).** The Vmp-loop, current-limit-loop, and+Vbatt-loop each produce an error voltage; a **1N4148 diode-OR** into a common node+(with a pull-down/pull-up appropriate to the chosen sense) ensures whichever loop is+*most restrictive* at any instant governs duty cycle — exactly the mechanism from the+Rev 1 architecture discussion, now built from discrete op-amp stages instead of an MCU.++**PWM generation — NE555 + LM393 comparator, no dedicated PWM IC.**+- NE555 configured as a free-running astable oscillator at **50kHz**+  (`f ≈ 1.44/((Ra+2Rb)C)`; standard component values chosen to hit this target,+  e.g. Ra=1kΩ, Rb=6.8kΩ, C=2.2nF gives ≈54kHz — close enough, fine-tuned at bring-up).+- Rather than the 555's square-wave output, its **timing-capacitor node** (pin 2/6) is+  used directly as the PWM ramp — a well-known basic-parts technique, avoiding a+  separate ramp generator.+- **LM393 comparator** compares this ramp against the combined (diode-OR'd) error+  voltage; output is the PWM gate-drive command.++**Gate driver.** A single small-signal NPN (**2N2222**) pulling the P-channel switch's+gate toward panel– when commanded on, with a 10kΩ gate pull-up (fail-safe OFF by+default, before the control loop is even running) and a 100Ω series gate resistor to+damp ringing.+- **Verify drive is adequate:** assumed P-FET gate charge Qg ≈ 20nC (typical for a+  power P-channel MOSFET at this current level); target transition time ~150ns for low+  switching loss at 50kHz → `I = Qg/t = 20nC/150ns ≈ 133mA`, comfortably within the+  2N2222's pulsed-current capability (500mA+).++### Block 3 — Primary buck conversion (charge stage power train)++**Topology decision, stated explicitly:** buck-only, not buck-boost. Charging a+~14.2V target requires Vin above roughly Vout plus margin — in practice, **useful+charging occurs only for Vin ≳ 15–16V.** Below that, the converter's duty cycle would+need to exceed 100%, which a buck cannot do — the converter simply delivers little or+no charge current, which is the same behavior any simple analog PWM solar charge+controller exhibits, and is not a fault. The stated 6–24V input range is honored as the+protection/survivability range (Block 1 components rated for it); the active-charging+range is the practical subset above ~15–16V. **This matches how real ~12V-class solar+panels are typically specified** (Vmp commonly 17–18V precisely to give this headroom).++**Switching frequency: 50kHz** — chosen as a basic-parts-friendly value: low enough for+clean switching with a simple discrete BJT gate driver and non-synchronous rectification,+high enough to keep the inductor/capacitors a reasonable physical size.++**Inductor.** Design current: charging current at full available power,+`Iout ≈ 30W × 0.9(est. eff.) / 14.2V ≈ 1.9A` → design point **2.0A average**, sized with+~25-30% ripple.+```+L = Vout(Vin−Vout) / (Vin × ΔIL × f)+At Vin=24V (worst case for ripple): L = 14.4×9.6/(24×0.6×50000) → chose L = 220µH+```+Verified across the range (computed, not assumed):++| Vin | Duty cycle | Ripple ΔIL | Peak inductor current |+|---|---|---|---|+| 24V | 0.59 | 0.53A | 2.26A |+| 18V | 0.79 | 0.27A | 2.14A |+| 16V | 0.89 | 0.15A | 2.07A |++**Inductor rating:** 220µH, **Isat ≥ 3A** (margin over the 2.26A worst-case peak),+low DCR (<100mΩ) for efficiency — a common shielded power inductor, not a specialty part.++**P-channel switch.** Worst-case continuous current 5.0A (input-referred, Block 1),+worst-case blocking voltage = worst-case Voc (~30V assumed, pending real panel spec).+**IRF4905** (55V, 74A, Rds(on)≈0.02Ω) selected — same part as the reverse-polarity FET+(BOM commonality). Conduction loss at 5A: `5²×0.02 = 0.5W`. Switching loss estimated+from the driver's ~150ns transition time at 50kHz, worst-case 24V×5A: roughly+`0.5 × V × I × (tr+tf) × f = 0.5×24×5×300ns×50000 ≈ 0.9W` — combined ~1.4W, requiring a+modest heatsink/copper-pour thermal path (flagged for the PCB-layout phase, not this one).++**Catch diode (non-synchronous — a second synchronous MOSFET was judged unnecessary+complexity for a basic-parts design at this power level).** Schottky, voltage rating+with margin above 30V assumed Voc, current rating covering the (1−D)-weighted average+plus ripple. **SS54 (40V, 5A) or a beefier equivalent (e.g. SB560, 60V/5A)** selected —+**60V/5A part recommended** for margin given Voc uncertainty. Forward-drop loss at+worst case: `Vf(≈0.5V) × Iavg(≈1.9A) × (1−0.59) ≈ 0.4W`.++**Output bulk/HF capacitance.** Feeding the battery, which itself dominates the output+impedance — modest local capacitance is sufficient: **2× 100µF low-ESR + 1µF ceramic**,+matching the input-side values (BOM commonality, and both need similar ripple-current+handling given the pulsed nature of a non-synchronous buck's output-diode current).++### Block 4 — 5V rail generation++**Simplified control vs. the charge stage**: no MPPT/Vin-loop needed — the battery is a+stiff source, so this is a conventional 2-loop (output voltage + current limit) basic-+parts buck, structurally identical to Block 3's power train and Block 2's control+techniques, reused for BOM commonality.++**Input range:** battery bus, assumed 10.5V (discharged) to 14.4V (during charge).+**Output:** 5.0V, 2.0A.++**Switching frequency:** 50kHz (matched to the charge stage — no synchronization is+attempted, but matching keeps EMI filtering/decoupling design consistent).++**Inductor.**+```+L = Vout(Vin−Vout)/(Vin×ΔIL×f), worst case at Vin=14.4V → chose L = 100µH+```+Verified:++| Vin | Duty cycle | Ripple ΔIL | Peak inductor current | Cin Irms |+|---|---|---|---|---|+| 14.4V | 0.35 | 0.65A | 2.33A | 0.95A |+| 12.0V | 0.42 | 0.58A | 2.29A | 0.99A |+| 10.5V | 0.48 | 0.52A | 2.26A | 1.00A |++**Inductor:** 100µH, Isat ≥ 3A, low DCR.++**P-channel switch:** much lower voltage stress than Block 3 (≤15V vs. ~30V) but+similar current (2.3A peak) — a smaller, cheaper part suffices: e.g. **Si2333DS+(30V, ~5A class, low Rds(on))** or, for simple through-hole BOM commonality with+Block 3, a smaller TO-220 P-channel part rated ≥30V/≥8A. Exact part TBD at+schematic/BOM finalization; rating targets stated here per the "verify voltage/current"+requirement.++**Catch diode:** 30V/5A Schottky (e.g. **SS34**), margin over the 14.4V max input.++**Output capacitance.** No battery-like buffering here — this feeds real load+electronics directly, so transient response matters more.+```+C_min (ripple term only) = ΔIL/(8×f×Vripple_target) = 0.65/(8×50000×0.05V) ≈ 32.6µF+```+Specified: **2× 47µF low-ESR (polymer or X7R ceramic) + 1µF ceramic HF decoupling**+(94µF total, comfortably above the 32.6µF minimum, with margin for load-transient+response given the absence of a battery buffer at this specific node).++**Current-limit sense:** same 0.05Ω/×20-gain scheme as Block 2, target limit **2.4A**+(20% headroom over 2A rated) — divider values computed in Block 2's table, reused here+against this stage's own zener reference (separate zener, same part, off the battery+bus rather than the panel-derived bias rail).++### Block 5 — 3.3V rail generation++**Derived from the 5V rail, not the 12V bus, and using a simple linear regulator —+justified, not a default choice.**+- A switching regulator here would be unnecessary complexity for very little gain：+  linear dissipation from 5V→3.3V at 1A is only `(5−3.3)×1 = 1.7W` — modest and+  thermally manageable. Deriving from **5V rather than 12V** is what keeps that+  dissipation small (12V→3.3V linear would waste `(12−3.3)×1 ≈ 8.7W`, unacceptable).+- **LM317** adjustable 3-terminal linear regulator selected — about as basic and+  universal an active regulation part as exists, satisfies "basic components" better+  than assembling a discrete pass-transistor regulator from raw parts (which would use+  *more* components for worse performance).+```+Vout = 1.25V × (1 + R2/R1); standard LM317 minimum load current ≈ 10mA (satisfied by R1)+Choosing R1 = 240Ω: R2 = R1×(Vout/1.25 − 1) = 240×(3.3/1.25 − 1) = 240×1.64 = 393.6Ω+→ use 390Ω (E96) → actual Vout = 1.25×(1+390/240) = 1.25×2.625 = 3.28V (verified)+```+Input/output capacitance per LM317 datasheet minimums: 0.1µF input ceramic (if regulator+is more than a few inches from the 5V rail's own bulk cap — here it's on the same+board, so this is a conservative-but-cheap addition) + 1µF output ceramic + 10µF+tantalum/electrolytic on the ADJ pin for ripple rejection (standard datasheet+application circuit).++### Block 6 — Output protection/filtering++- Small ferrite bead + local ceramic decoupling at each output connector (5V, 3.3V),+  standard practice for conducted-emissions cleanup, not separately calculated (values+  are catalog-standard, e.g. 600Ω@100MHz bead + 100nF).+- A series Schottky "OR-ing"-style protection is **not** added on the output rails+  themselves (unlike the input) — there is no reverse-feed risk here since these are+  simple point-of-load outputs, not paralleled sources.++### Block 7 — Voltage/current monitoring++Separate from Block 2's internal control-loop sensing: these are **buffered,+scaled analog outputs** for external measurement, using the LM324's spare sections+(each converter's control quad has one section left over after Vmp/Ilimit/summing use).+- Battery voltage monitor: buffered divider tap (reusing the Block 2 Vbatt-sense+  network through a unity-gain buffer, so external test equipment doesn't load the+  precision divider).+- Charge current monitor: buffered output of the ×20 current-sense amplifier+  (0.11V/A scale at the shunt, reusing the same op-amp section from Block 2 rather than+  a duplicate — one signal serves both the control loop and the monitor test point).++### Block 8 — Test points and connectors++Test points planned at: panel+ (post-fuse), panel– /GND reference, battery+, 5V rail,+3.3V rail, Vmp-sense divider tap, Vbatt-sense divider tap, current-monitor output,+PWM gate-drive signal (each converter), 555 ramp node (each converter).+Connectors: solar-panel input (2-pin), battery (2-pin), 5V output, 3.3V output,+common ground reference.++---++## Summary table — key calculated values++| Parameter | Value | Basis |+|---|---|---|+| Fuse | 6.3A fast-blow | 30W/6V = 5.0A worst case + margin |+| Charge-stage L | 220µH, Isat≥3A | ripple calc @ Vin=24V worst case |+| Charge-stage Ilimit | ~2.2A | 0.05Ω shunt, ×20 gain, 15% headroom over 1.9A |+| Battery CV setpoint | 14.10V (target 14.2V) | TL431 + 46.4k/10k divider |+| Vmp sense trip | 18.10V (target 18V, adjustable) | zener ref + 25.5k/10k divider |+| 5V-stage L | 100µH, Isat≥3A | ripple calc @ Vin=14.4V worst case |+| 5V-stage Ilimit | ~2.4A | 0.05Ω shunt, ×20 gain, 20% headroom over 2A |+| 3.3V regulator | LM317, R1=240Ω, R2=390Ω | 3.28V actual (verified) |+| Switching frequency | 50kHz (both stages) | NE555 astable, basic-parts friendly |++## Open items carried forward from Rev 1 (still unresolved)++1. Real panel Voc and its temperature coefficient — needed to finalize TVS/FET voltage+   ratings (currently using an assumed 30V worst case).+2. Confirm battery chemistry (SLA/AGM assumed) — affects the 14.2V CV setpoint if a+   different chemistry is actually used.+3. The housekeeping bias zener (Block 2) has non-trivial no-load power dissipation at+   worst-case Voc — will be implemented as an NPN emitter-follower regulator (not a bare+   zener) in the schematic to keep this reasonable; flagged here so the reasoning is+   visible before you see it in the schematic.

@@ -0,0 +1,87 @@+# Solar MPPT Charge System — Schematic Completion Summary++**File:** `mppt-power-system.kicad_sch` (+ matching `.kicad_pro`)+**ERC result: 0 errors, 0 warnings.**+**Status: schematic complete and reviewed. PCB layout has NOT been started, per instruction.**++## What this schematic is++A discrete-analog solar MPPT battery charger + POL regulator system, built with+**no MCU and no dedicated MPPT/buck-boost-controller/current-sense ICs** — every+control function (MPPT approximation, CV/CC charging, output regulation) is built+from generic, multi-sourced basic parts: LM324 op-amps, an LM393 comparator, TL431+shunt references, NE555 timers used as ramp generators, discrete P-channel power+MOSFETs, and Schottky/zener/signal diodes. Full engineering justification for every+choice is in `02-detailed-design-calculations.md`.++## Component count++45 references, ~150 individual parts (many resistors/caps), across:++| Block | Contents |+|---|---|+| 1. Solar input & protection | Connector, fuse, reverse-polarity P-FET, TVS, bulk/HF caps |+| 2. MPPT sensing/control | Housekeeping bias reg, 5.1V ref, Vmp divider, current-sense diff-amp, TL431 CV loop, diode-OR combiner, NE555 ramp, LM393 PWM compare, gate driver |+| 3. Primary buck conversion | Charge-stage P-FET switch, catch diode, 220µH inductor, output caps (feeds VBATT) |+| 4. 5V rail generation | Same control architecture as Block 2, simplified to 2 loops (no MPPT/Vin loop needed - battery is a stiff source); own 100µH buck power train |+| 5. 3.3V rail | LM317 linear regulator from the 5V rail (justified: 1.7W dissipation is small, avoids an unneeded second switcher) |+| 6. Output protection/filtering | Ferrite bead + decoupling on each output rail |+| 7. Monitoring | Buffered VBATT/V5V taps + already-buffered current-sense amplifier outputs, using spare LM324 sections (no added ICs) |+| 8. Test points & connectors | 16 labeled test points, 4 connectors (solar in, battery, 5V out, 3.3V out) |++## Real bugs found and fixed during generation (worth recording)++1. **Rotation-transform bug (mine):** placing a symbol with `rot=90` without also+   rotating its pin-offset math put ~150 pin labels at the wrong coordinates.+   Fixed by keeping all passives at `rot=0` (cosmetic only — does not affect any+   electrical value).+2. **NE555 "unit 0" misunderstanding:** KiCad's convention for a symbol's "unit 0"+   sub-part is pins *common to every real unit* (here, the 555's shared GND/VCC),+   not an independently placeable unit. Treating it as a normal separate unit left+   the timer's own functional pins electrically orphaned. Fixed generally in the+   symbol-library reader (merges unit 0 into every real unit), not just for this+   one part.+3. **A gate-drive design error caught before it reached the schematic**: an initial+   "pull the P-FET gate toward its own source" driver plan would not have fully+   enhanced the FET; "pull toward ground" alone risked exceeding the FET's Vgs+   rating at high panel voltage. Resolved with a gate-source zener clamp (present+   in both switching stages), same technique already used for the reverse-polarity+   FET.+4. **A units-count error I caught and corrected while writing the calculations**:+   the charge-stage catch diode's rating was overstated (5A) based on confusing+   input current with diode current — the diode only ever carries inductor current+   (≤2.3A peak, <1A average), so a 3A-rated Schottky (SS36) is correct, not 5A.++## Design decisions made explicit (not silently assumed)++- Charge stage is **buck-only**, not buck-boost, despite the original brief.+  Charging ~14.2V requires Vin ≳ 15-16V regardless of topology, so a buck-boost's+  extra half-bridge bought nothing here — see Block 3 in the calculations doc for+  the full reasoning and what happens below that threshold (expected near-zero+  charge current, not a fault).+- 3.3V derived from 5V via a simple linear regulator, per your instruction to+  avoid unneeded converter complexity where the efficiency cost is small.+- LM393's open-collector outputs are pulled up; unused comparator/op-amp channels+  are explicitly tied off (inputs to GND, outputs no-connected) rather than left+  floating, to keep ERC meaningful rather than suppressed.++## Open items (carried from the calculations doc, still unresolved)++1. Real panel Voc and its temperature coefficient — TVS/FET voltage ratings use an+   assumed 30V worst case pending the actual panel datasheet.+2. Battery chemistry assumed SLA/AGM (14.2V CV target) — confirm, since a different+   chemistry would shift this setpoint.+3. Control-loop stability (the diode-OR combiner's transition behavior between+   loops) is a bench-verification item, not something hand calculation or this+   schematic capture can fully settle.+4. Cosmetic only: at full-page zoom-to-fit, adjacent blocks' header text can appear+   to visually run together on screen — verified this is a rendering artifact of+   viewing many small text objects at extreme zoom-out, not an actual coordinate+   collision (checked programmatically: zero conflicting label positions in the+   file). Zooming into any individual block shows its labels clearly.++## Explicitly not done, per instruction++- No PCB layout, no footprint-to-PCB placement, no routing.+- No footprint verification beyond making the Footprint field populated and valid+  for later PCB-layout use — package/footprint choice can be revisited then.

@@ -0,0 +1,198 @@+# Solar MPPT Charge System — PCB Layout Review++**Board:** `mppt-power-system.kicad_pcb`, 4-layer, 250mm x 160mm+**DRC: 0 errors.** 66 remaining warnings, all cosmetic/informational (footprint+library-link notices, mounting-hole "not in schematic" flags, silkscreen+legibility) — none electrical. Full breakdown in the "Known non-electrical+warnings" section at the end.+**Routing: 58/58 nets, 776 track segments, 150 vias.**++---++## Layer stack and why++F.Cu (components + power routing) / **In1.Cu solid GND plane** / In2.Cu (signal+routing + a few power bridges) / B.Cu (return routing + reinforcing GND pour).++Chosen over 2 layers because this board has two real switching converters with+genuine dI/dt loops, a Kelvin current-sense scheme that needs isolation from+switching noise, and an explicit ask to separate power and sensing grounds. A+dedicated inner plane is what actually delivers a low-impedance return path+directly beneath every forward trace — that's not available on 2 layers+without giving up something else this design needed.++---++## 1. Switching-loop geometry++**What was hand-placed vs. autorouted, and why:** the two power stages'+Q(switch)–D(catch)–L(inductor)–C(local decoupling) clusters were placed and+routed by hand, first. Everything else (control-circuit interconnects, the+bulk of the sense-signal routing) was left to the autorouter, because loop+area doesn't matter there the way it does at the switch node.++**Charge-stage loop** (Q4/D9/L1/C20, around board coords x:50-95, y:45-65):+- The fast-edge commutation loop is C20(local HF cap) → Q4(S→D) → D9(K→A) →+  back to C20's ground. C20 sits immediately upstream of Q4's source, placed+  there specifically so the high-frequency ripple current the switch demands+  each cycle is supplied **locally**, not pulled back through the current-sense+  shunt (RS1) or the bulk input capacitors 20-30mm away — pulling it through+  the shunt would have both enlarged the effective loop and injected+  switching-frequency noise directly onto the MPPT current-sense signal.+- D9's anode and C20's ground pin each drop a **dedicated via straight into+  the In1.Cu plane** rather than being tied together by a routed trace. At+  this power level a short via into a solid plane is a lower-inductance return+  path than any practical hand-routed trace between two THT/SMD footprints+  spaced this far apart — this is the one place the 4-layer stack directly+  pays for itself in loop-area terms, not just "having a ground layer."+- The switch node (Q4 drain → D9 cathode → L1) is routed as a single ~1.2mm+  trace with two deliberate jogs (around Q4's own gate pin and D9's anode,+  both of which sit in-line with the direct path) — kept to the minimum length+  the TO-220/SMC package geometry allows, not padded out further.+- **Honest caveat:** Q4 and Q1 are TO-220 through-hole parts, chosen+  specifically for easy heatsinking and hand assembly. That is a real+  trade-off against loop tightness — TO-220 pin spacing (2.54mm centers, ~10mm+  body) puts a floor under how small this loop can get that an all-SMD design+  in a QFN or SO-8 wouldn't have. If EMI testing on a prototype shows this+  matters in practice, the fix is a component-level respin (SMD switch ++  SMD Schottky in a tighter footprint), not a layout tweak — I'm stating that+  plainly rather than overclaiming the loop is as tight as physically possible.++**5V-stage loop** (Q10/D14/L2/C21): identical topology and reasoning, at+lower voltage stress (≤15V vs. ~30V worst case) and the same current class.++## 2. Kelvin current sensing++Both shunts (RS1 for the charge stage, RS2 for the 5V stage) have their+sense taps originate **at the shunt's own pads**, not at some other point+along the shared power net — the defining requirement for Kelvin accuracy.+The charge-stage pair was hand-routed on **In2.Cu**, physically off the top+layer and clear of every switching trace, specifically so switching-edge+coupling doesn't ride in on the sense signal before it reaches the+differential amplifier. The 5V-stage pair's final short hop was left to the+autorouter after several manual attempts hit dense pre-existing copper near+that comparator; I verified afterward that the resulting path does not run+through or alongside the switch-node traces.++## 3. Thermal performance++Calculated worst-case dissipation (from the design-calculations doc):+Q4 ≈1.4W (conduction + switching loss at Vin=24V/5A), Q1 ≈0.5W, Q10 lower+(reduced voltage stress). These are **modest**, not extreme, figures.++- TO-220 packages were chosen partly because they accept a bolt-on heatsink+  if a real prototype shows more margin is needed — that option was+  deliberately preserved rather than closed off by an SMD choice.+- **No dedicated thermal vias were added.** At these calculated dissipation+  levels, and given the drain/tab-equivalent pin already sits on a routed+  copper net, I judged extra vias weren't clearly justified over adding+  copper to the switch node (which would work against the EMI goal directly+  above it) — a deliberate trade-off, not an oversight. If bench testing on a+  prototype shows a specific device running hotter than the calculation+  predicts, the fix is a small dedicated copper island on an inner layer tied+  to that device's source pad (a quiet net, not the switch node) with a+  handful of vias — a straightforward addition once real thermal data exists+  to size it against, which hand calculation alone can't fully substitute for.++## 4. Current capacity++Per the design-calculations doc's worst-case figures: ~5.0A at the panel+input (before the current-sense shunt), ~2.3A peak in each inductor loop,+2A/1A at the 5V/3.3V outputs.++- PANEL_P_RAW/PANEL_P_FUSED/PANEL_P_PROT (the 5A-class path) and the+  switching-loop nets (VIN_CHG/SW_CHG/VBATT/VIN_5V/SW_5V/V5V_RAIL) were+  hand-routed at 1.0-1.2mm trace width, comfortably covering their respective+  current classes on an external copper layer with real margin.+- Everything else picked up the board's **default net class width, raised to+  1.0mm** before autorouting — deliberately generous for a mixed-signal+  board, so nets that happen to sit on a higher-current path (e.g. V5V_RAIL's+  branches to the output connector) aren't left at a thin, signal-only+  default just because they were autorouted rather than hand-placed.+- The current-sense shunts themselves (0.05Ω, sized in the calculations doc+  for I²R and signal-resolution reasons) are 2512-size resistors, rated for+  the worst-case current with margin.++## 5. Grounding++**One solid ground plane (In1.Cu), not split analog/power planes** — a+deliberate choice, not a shortcut. Splitting ground planes was common+1990s-2000s guidance; modern practice generally avoids it, because a moat cut+into a plane forces return current to detour around the gap, which can act as+a slot antenna and *increase* radiated EMI rather than reduce noise coupling.+Instead, "separate noisy power ground from sensitive analog sensing" is+implemented here through **placement and routing discipline**: the control+circuitry (both stages) sits physically set back from its switching loop by a+real gap, and the two Kelvin sense pairs are routed on an inner layer,+specifically to keep their return current from sharing a path with the+switching loop's return current on the solid plane — the plane's low+impedance does the rest.++A second GND pour was also placed on B.Cu, reinforcing the return path and+giving surface-mount ground pins (which don't reach In1.Cu on their own) a+second, shorter route to a plane via a stitching via.++**Genuinely known limitation:** the reinforcing B.Cu pour is also used for a+handful of hand-routed power and sense traces in this design (routed there+specifically to get them off the congested top layer). Those traces coexist+with the GND pour on the same layer — which is normal practice (KiCad clears+plane copper around any differently-netted trace automatically) — but it does+mean B.Cu isn't a pristine, trace-free return plane the way In1.Cu is. In1.Cu+is the layer actually doing the return-path work described above.++## 6. EMI risk++- **Primary radiator risk**: the two switch-node copper runs (SW_CHG, SW_5V),+  since they swing the full input/battery voltage at the switching edge rate.+  Kept to single, minimum-length, appropriately-sized traces rather than+  wide copper, per the explicit "switch-node copper only as large as+  necessary" requirement — a wider switch-node pour would be a *worse* EMI+  choice here even though it looks more robust, because it increases the+  radiating area at exactly the node with the fastest edges.+- **Secondary risk**: gate-drive traces (GATE_CHG, GATE_5V) also carry fast+  edges, at lower voltage swing than the switch node itself. These were kept+  short (routed directly beside their FET) but were not separately isolated+  from the sense-signal routing region the way the switch-node/Kelvin split+  was — worth a closer look if a prototype shows more gate ringing than+  expected.+- **Mitigated by construction**: the solid In1.Cu plane under the entire+  switching-loop area gives every fast-edge trace a tight, direct image+  return current path immediately beneath it, which is the single biggest+  lever against loop-radiated EMI available at the layout stage — bigger than+  any local placement tweak.+- **Not evaluated here**: actual radiated/conducted emissions depend on real+  component parasitics, gate drive rise/fall times, and enclosure/cabling,+  none of which layout alone determines. This review covers what the layout+  controls; a real EMI compliance assessment needs bench measurement on a+  built prototype.++---++## Known non-electrical DRC warnings (0 errors; these are the remaining 66 warnings)++- **footprint_symbol_mismatch / lib_footprint_mismatch (34 combined)**: minor+  attribute differences (e.g. "exclude from BOM" flag) between the embedded+  footprint copy and the current state of the installed library, plus the+  hand-authored mounting-hole footprint not being a byte-for-byte match to+  KiCad's own library copy. Cosmetic bookkeeping, not a fabrication issue.+- **extra_footprint (4)**: the four mounting holes — legitimately absent from+  the schematic (they're a PCB-only mechanical feature), so this flag is+  expected and standard for any board with mounting holes.+- **silk_overlap / silk_over_copper (17 combined)**: reference-designator+  legibility on a few densely-packed 0805/SOIC parts. Doesn't affect+  fabrication or assembly, worth a pass in the PCB editor before production+  if silkscreen readability matters for hand assembly.+- **isolated_copper (7)**: small disconnected copper-fill islands within the+  GND zone, in areas boxed in by other nets. Expected byproduct of a solid+  pour around dense routing; each is tiny and non-functional either way.++## What to do before fabrication++1. Confirm the real panel's Voc and its temperature coefficient (still an+   open item from the schematic phase) — affects input protection component+   ratings, not the layout itself.+2. A final visual pass in the PCB editor on silkscreen legibility near the+   densest clusters (Zone B control circuitry, the 5V-stage comparator).+3. If a prototype's thermal measurements show more margin is needed at Q4,+   add the source-side thermal-via island described in Section 3 — a+   contained addition, not a re-layout.

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