Loads on click. Unloads when scrolled away or the tab is hidden.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

PCB Footprint

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Loads on click. Unloads when scrolled away or the tab is hidden.
Download PDF
Contents

README

markdown

ZD24C16A-SSGMB

Zetta · EEPROM · SOP-8

ZD24C16A-SSGMB from Zetta, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No Connect. Not bonded to a die pad. May be tied to GND or left floating. On the 16K variant the A2/A1/A0 hardware address pins are unused because all three device-address bits are consumed for memory page addressing.
2 NC unconnected No Connect. Not bonded to a die pad. May be tied to GND or left floating. On the 16K variant the A2/A1/A0 hardware address pins are unused because all three device-address bits are consumed for memory page addressing.
3 NC unconnected No Connect. Not bonded to a die pad. May be tied to GND or left floating. On the 16K variant the A2/A1/A0 hardware address pins are unused because all three device-address bits are consumed for memory page addressing.
4 GND power_in Ground reference for the power supply. Connect to system ground.
5 SDA bidirectional Serial Data. Open-drain bidirectional I2C data line used to serially transfer data to and from the device. Must be pulled high with an external pull-up resistor (not to exceed 10 kOhm) and may be wire-ORed with other open-drain devices on the same bus.
6 SCL input Serial Clock. Provides the I2C clock to the device and controls data flow. Data on SDA is latched on the rising edge of SCL and output on the falling edge. Must be pulled high externally or forced high when the bus is idle.
7 WP input Write Protect (asserted high). Tie to GND for normal read/write operation. When connected to VCC, all write operations to the memory array are inhibited. Internally pulled down to GND if left undriven, but Zetta recommends driving to a known state.
8 VCC power_in Device power supply. Provides source voltage to the chip. Operation at invalid VCC levels may produce spurious results.

Key specifications

Parameter Value
Manufacturer Zetta
Package SOP-8
Category Memory
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • ZD24C16A-SSGMB

CAD (KiCad official)

  • Symbol: ZD24C16A-SSGMB
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Zetta datasheet (22 pp, sha256 b348afafa94d42a8, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF