XT2052Y2ASR-G from NATLINEAR, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	No internal connection. Leave floating or tie to GND for improved layout.
2	ISET	input	Charge-current program, monitor and shutdown pin. Charge current is set by a 1% resistor to GND: IBAT = (VISET/RISET) × 1000. In constant-current mode VISET ≈ 1.0V. Pulling ISET above 1.21V (via a 3µA internal pull-up when RISET is disconnected) puts the charger into shutdown (Icc drops to ~25µA); clamp voltage ≈ 2.4V. Reconnecting RISET to GND resumes normal operation.
3	GND	power_in	Device ground. The EXPOSED PAD on the bottom of the package must also be tied to pin 3 / GND for proper operation and thermal dissipation.
4	VIN	power_in	Positive supply input, 4.25V-6.5V operating (absolute max 7V; OVP trips above 6.8V). Requires at least a 1µF bypass capacitor. When VIN falls to within 30mV of VBAT the charger stops and BAT-pin drain drops below 0.1µA.
5	VBAT	power_out	Battery connection to the single-cell Li-ion pack positive terminal. Regulated float voltage 4.2V (±1%). When charging is complete and VIN is present, BAT draws ~2µA; if VIN is removed BAT draws <0.1µA (reverse-blocked). A ≥4.7µF capacitor on this pin is required for stable operation and no-battery detection.
6	DONE	output	Open-drain charge-complete status output. Pulled low by an internal NMOS when the charge cycle finishes (VOL ≈ 0.35V at 5mA); high-impedance otherwise. Can directly drive an LED or a microcontroller input.
7	CHRG	output	Open-drain charge-in-progress status output. Pulled low by an internal NMOS while the battery is being charged (VOL ≈ 0.35V at 5mA); high-impedance otherwise. Pulses at ~2Hz (with 4.7µF on BAT) to indicate the no-battery condition.
8	NC	unconnected	No internal connection. Leave floating or tie to GND for improved layout.
EP	EPAD	power_in	Exposed thermal pad on the underside of the package. Must be soldered to the GND copper plane and tied to pin 3 for proper thermal performance, especially in high-current (up to 1.0A / 1.2A) applications.

Key specifications

Parameter	Value
Manufacturer	NATLINEAR
Package	SOP-8-EP
Category	PMIC
Pins	9

Ordering variants

Same part, different packaging or reel option.

XT2052Y2ASR-G
XT2052Y2ASR-GSL
XT2052Y2ASR-GQR
XT2052Y2ASR-GQL

CAD (KiCad official)

Symbol: XT2052Y2ASR-G
Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm
3D model: SOP-8-EP (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`xt2052y2asr-g.step`	193 KB	You want the bare part, or you mark your own boards.
`xt2052y2asr-g-etched.step`	2.2 MB	You want the part with `XT2052Y2ASR-G` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 560 faces against 63 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: NATLINEAR datasheet (9 pp, sha256 13ed9ecb9230a2aa, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF