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XL3843

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by Ray

XINLUDA AC-DC Controllers and Regulators, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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XL3843

XINLUDA · AC-DC Controllers and Regulators · SOP-8

XL3843 from XINLUDA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COMP output Error Amplifier output, made available for external loop compensation. Connect a Zf feedback network from COMP to VFB (pin 2) to shape the control loop. Also serves as the internal PWM control input (clamped ~1 V above VFB via internal 2R/R divider and diode).
2 VFB input Inverting input of the internal Error Amplifier (non-inverting input is tied to the internal 2.50 V reference). Normally connected to the switching regulator output through a resistor divider to set the regulation setpoint. Input bias current typ. -0.1 uA.
3 ISENSE input Current-sense input. A voltage proportional to the switch/inductor current (typically from a source-side sense resistor) is applied here; the PWM comparator terminates the output pulse when this input reaches the level set by COMP (max input 1 V, clamped internally). Gain from VFB to ISENSE trip is ~3 V/V.
4 RT/CT passive Oscillator timing pin. Connect RT from VREF (pin 8) to this pin and CT from this pin to GROUND to program oscillator frequency and maximum duty cycle. Operation up to 500 kHz is possible. Peak-to-peak oscillator swing ~1.6 V; discharge current typ. 8.3 mA.
5 GROUND power_in Combined control-circuitry and power ground reference for the IC. All voltages in the datasheet are referenced to this pin. Use single-point grounding with timing/bypass caps returned close to pin 5 because of high peak gate-drive currents.
6 OUTPUT output Totem-pole gate-driver output that directly drives the gate of an external N-channel power MOSFET. Sources and sinks up to ±1 A peak (average 200 mA). VOH ~13.5 V at 20 mA source; VOL ~0.1 V at 20 mA sink; typical rise/fall time 50 ns into 1 nF. Output is held low during UVLO.
7 VCC power_in Positive supply for the control IC. Recommended operating range 12-28 V; abs max 30 V. Internal 34 V zener clamp. For the XL3843, UVLO start (on) threshold is 8.4 V typ. and turn-off is 7.6 V typ. Startup current <0.5 mA. Bypass locally to GROUND with a low-ESR capacitor.
8 VREF power_out Buffered 5.00 V ±1% precision reference output. Supplies the RT charging current for CT via RT and can source up to ~20 mA to external circuitry. Short-circuit current typ. -100 mA. Bypass with ~0.1 uF to GROUND close to the pin.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package SOP-8
Category PMIC
Pins 8

CAD (KiCad official)

  • Symbol: XL3843
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (17 pp, sha256 33b5061601fe0cec, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF