W25Q32JV
Public Unreviewedby Ray
Winbond 32 Mbit (4 MB) serial NOR flash, SOIC-8. Standard/Dual/Quad SPI, 133 MHz, 4 KB sectors. Datasheet-verified.
3D Model
Open in new tab ↗
Symbol & Footprint
Schematic Symbol
Open full view ↗PCB Footprint
Open full view ↗Datasheet
Open in new tab ↗README
markdownW25Q32JV
Winbond · 32 Mbit SPI NOR flash · SOIC-8 (208 mil)
A 32 Mbit (4 MB) serial NOR flash from the Winbond W25Q family, in the wide SOIC-8, sized for firmware, fonts, and file systems on smaller designs than the 128 Mbit W25Q128 needs. It speaks Standard, Dual, and Quad SPI plus QPI at up to 133 MHz (a 532 MHz-equivalent throughput in Quad), organizes the array in uniform 4 KB erasable sectors, and its six SPI pins double as the four data lines in Quad mode. A single 2.7-3.6 V supply and 100k-cycle endurance make it a drop-in external storage for MCUs, FPGAs, and ESP modules.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | /CS | input | Chip Select input (active-low). Drive low to enable the device and begin an SPI transaction; drive high to deselect and place DO/IO pins in high-impedance. Requires a full high-to-low transition after power-up before the first instruction; a pull-up resistor is recommended. |
| 2 | DO (IO1) | bidirectional | Standard SPI serial Data Output; also acts as bidirectional IO1 for Dual/Quad SPI operations. Data is shifted out on the falling edge of CLK in Standard SPI; in Dual/Quad modes it functions as a bidirectional data line. |
| 3 | /WP (IO2) | bidirectional | Active-low Write Protect input for the Status Register in Standard/Dual SPI mode; reassigned as bidirectional IO2 when the Quad Enable (QE) bit in Status Register-2 is set for Quad SPI operations. |
| 4 | GND | power_in | Ground reference for the device supply. |
| 5 | DI (IO0) | bidirectional | Standard SPI serial Data Input; also acts as bidirectional IO0 for Dual/Quad SPI operations. Instructions, addresses, and data are latched on the rising edge of CLK. |
| 6 | CLK | input | SPI Serial Clock input providing the timing for all serial input and output operations. Supports up to 133 MHz; SPI Mode 0 (0,0) and Mode 3 (1,1) are supported. |
| 7 | /HOLD or /RESET (IO3) | bidirectional | Active-low Hold input (or optional Reset input, ordering-code dependent) in Standard/Dual SPI mode; reassigned as bidirectional IO3 when Quad Enable (QE) is set. /HOLD pauses serial communication without deselecting the device. |
| 8 | VCC | power_in | Positive power supply, 2.7 V to 3.6 V. Must track above the power-on threshold before /CS is driven low. |
Key specifications
| Parameter | Value |
|---|---|
| Type | Serial NOR flash memory |
| Density | 32 Mbit (4 MB) |
| Interface | Standard / Dual / Quad SPI + QPI |
| Max clock | 133 MHz |
| Erase granularity | 4 KB sector (uniform) |
| Endurance | 100k erase/program cycles |
| Supply voltage | 2.7-3.6 V |
| Package | SOIC-8 (208 mil) |
Ordering variants
Same part, different packaging or reel option.
W25Q32JVSSIQ (SOIC-8, 208 mil)W25Q32JVZPIQ (WSON-8)
CAD (KiCad official)
- Symbol:
Memory_Flash:W25Q32JVSS - Footprint:
Package_SO:SOIC-8_5.3x5.3mm_P1.27mm - 3D model: SOIC-8 208 mil (KiCad packages3D)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Winbond datasheet (16 pp, sha256
16abfa1952dadcdb, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).