UCC28C43DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	COMP	output	Error amplifier output used for loop compensation. Frequently used as a control port by driving via a secondary-side opto-isolator; the error amplifier is internally current limited so forcing COMP to GND commands zero duty cycle.
2	FB	input	Inverting input to the internal error amplifier used to control the power converter voltage-feedback loop for stability. The non-inverting input is internally trimmed to 2.5V ± 1%.
3	CS	input	Primary-side current sense input (non-inverting input to the PWM comparator). Connect to the current-sense resistor; when this signal exceeds the scaled error-amplifier voltage the PWM terminates OUT conduction. A voltage ramp may be applied here for voltage-mode operation. COMP-to-CS offset ≈ 1.15V, max CS input signal ≈ 1V.
4	RT/CT	bidirectional	Fixed-frequency oscillator timing node. Connect timing resistor R_RT from VREF to this pin and timing capacitor C_CT from this pin to GND to set switching frequency (fSW = fOSC for the C43). Peak-to-peak ramp ≈ 1.9V; internal discharge current ≈ 8.4mA (with R_RT = 10kΩ).
5	GND	power_in	Ground return pin for the output driver stage and the logic-level controller section. All voltages are referenced to this pin.
6	OUT	output	High-current totem-pole gate-drive output intended to directly drive an external MOSFET gate. Rail-to-rail ±1A peak (source/sink), 25ns rise / 20ns fall into 1nF; runs at the oscillator frequency with up to ~100% duty cycle for the UCC28C43. OUT is actively held low when VDD is below the turn-on threshold.
7	VDD	power_in	Analog controller bias supply input (recommended operating range up to 18V, absolute max 20V). Requires a 0.1µF bypass to GND with minimal trace length and additional bulk capacitance ≥ 10× the external MOSFET gate capacitance. UVLO turn-on 8.4V / turn-off 7.6V (C43 variant); startup current 50µA typ, operating current 2.3mA typ.
8	VREF	power_out	5V ±1% precision reference output used to source oscillator timing current through R_RT and to power light external loads (up to 20mA source). Must be bypassed to GND with at least a 0.1µF ceramic located close to the pin for stability.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	PMIC
Pins	8

Ordering variants

Same part, different packaging or reel option.

UCC28C43DRD
UCC28C43DR
UCC28C43DRDGK
UCC28C43DRDGKR

CAD (KiCad official)

Symbol: UCC28C43DR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`ucc28c43dr.step`	122 KB	You want the bare part, or you mark your own boards.
`ucc28c43dr-etched.step`	2.5 MB	You want the part with `UCC28C43DR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 584 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (60 pp, sha256 9fa55f996731c56b, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF