UCC28180DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Device ground reference. All voltages in the datasheet are referenced to this pin.
2	ICOMP	output	Current loop compensation: transconductance current amplifier output. A capacitor connected to GND provides compensation and averaging of the current sense signal in the current control loop. The controller is disabled if the voltage on ICOMP is less than 0.2 V (ICOMPP protection).
3	ISENSE	input	Inductor current sense input. Reads the voltage across the external current sense resistor representing the instantaneous PFC boost inductor current. Soft Over Current (SOC) threshold approximately -0.285 V; cycle-by-cycle peak current limit (PCL) approximately -0.4 V. A 2.3-uA internal current source pulls ISENSE above 0.085 V to shut down PFC (ISOP protection) if the pin is open. Use a 220-Ohm series resistor to limit inrush currents into this pin.
4	FREQ	output	Switching frequency setting pin. Connect a resistor from FREQ to GND to program the operating switching frequency. Programmable range 18 kHz to 250 kHz; pin voltage typically 1.5 V.
5	VCOMP	output	Voltage loop compensation: transconductance voltage error amplifier output. An external RC network from VCOMP to GND sets loop compensation and soft start. VCOMP is held at GND until VCC exceeds its threshold and VSENSE reaches nominal regulation. Enhanced Dynamic Response (EDR) applies a higher transconductance for faster transient response. VCOMP is pulled low during VCC UVLO, OLP/Standby, ICOMPP and ISOP conditions.
6	VSENSE	input	Output voltage sense. An external resistor divider from the PFC boost output to VSENSE provides feedback regulation to the internal 5-V reference. A small capacitor to GND filters HF noise. Pulling VSENSE below 0.82 V (16.5% VREF, OLP threshold) enters standby and discharges VCOMP. A 100-nA internal current source pulls VSENSE to GND if disconnected. EDR, OVP (~107% and ~109% VREF) and open-loop protection are all triggered from this pin.
7	VCC	power_in	Device bias supply. Under-Voltage Lockout (UVLO) disables the controller until VCC exceeds the turn-on threshold of typically 11.5 V (max 12.1 V); operation continues until VCC falls below the turn-off (UVLO) threshold of typically 9.5 V. Absolute-max 22 V; recommended operating up to 21 V. Bypass with a 0.1-uF ceramic capacitor to GND as close to the device as possible for HF filtering of the VCC voltage.
8	GATE	output	Gate drive: integrated push-pull gate driver for one or more external power MOSFETs or IGBTs. Typical 2.0-A sink and 1.5-A source capability. Output voltage is clamped at typically 15.2 V. Absolute maximum on this pin is 22 V referenced to GND.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	PMIC
Pins	8

Ordering variants

Same part, different packaging or reel option.

UCC28180DR
UCC28180DRD

CAD (KiCad official)

Symbol: UCC28180DR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (48 pp, sha256 e1e1588c6854b437, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF