8-bit non-inverting bidirectional voltage-level translator with automatic direction sensing, in a TSSOP-20 package. It shifts eight signals between any two of the 1.5, 1.8, 2.5, 3.3, and 5 V rails (VCCA 1.4-3.6 V, VCCB 1.65-5.5 V), with no direction pin, so it Just Works on I2C, SPI, and GPIO between a 3.3 V MCU and 5 V peripherals. An OE pin puts all I/Os in high-Z. The default bus level shifter.

Pinout

Pin	Name	Type	Function
1	A1	bidirectional	A-port channel 1 I/O, referenced to VCCA. Auto-sensing bidirectional level-shifted data line paired with B1. Requires an external pull-up at each end for open-drain operation; drives push-pull otherwise.
2	VCCA	power_in	A-port supply rail. 1.4V ≤ VCCA ≤ 3.6V and VCCA ≤ VCCB. Sets the logic level for the A-side channels and OE input. Bypass locally with 0.1µF.
3	A2	bidirectional	A-port channel 2 I/O, referenced to VCCA. Paired with B2 for auto-sensing bidirectional level shifting.
4	A3	bidirectional	A-port channel 3 I/O, referenced to VCCA. Paired with B3.
5	A4	bidirectional	A-port channel 4 I/O, referenced to VCCA. Paired with B4.
6	A5	bidirectional	A-port channel 5 I/O, referenced to VCCA. Paired with B5.
7	A6	bidirectional	A-port channel 6 I/O, referenced to VCCA. Paired with B6.
8	A7	bidirectional	A-port channel 7 I/O, referenced to VCCA. Paired with B7.
9	A8	bidirectional	A-port channel 8 I/O, referenced to VCCA. Paired with B8.
10	OE	input	Output-enable. Referenced to VCCA. Drive high to enable translation on all 8 channels; drive low to place every A and B channel in the high-impedance (Hi-Z) state. Tie to GND through a pull-down during power-up/down to keep the device in Hi-Z (VIH ≥ 0.65·VCCA, VIL ≤ 0.35·VCCA).
11	GND	power_in	Device ground. Connect to the system ground reference.
12	B8	bidirectional	B-port channel 8 I/O, referenced to VCCB. Paired with A8.
13	B7	bidirectional	B-port channel 7 I/O, referenced to VCCB. Paired with A7.
14	B6	bidirectional	B-port channel 6 I/O, referenced to VCCB. Paired with A6.
15	B5	bidirectional	B-port channel 5 I/O, referenced to VCCB. Paired with A5.
16	B4	bidirectional	B-port channel 4 I/O, referenced to VCCB. Paired with A4.
17	B3	bidirectional	B-port channel 3 I/O, referenced to VCCB. Paired with A3.
18	B2	bidirectional	B-port channel 2 I/O, referenced to VCCB. Paired with A2.
19	VCCB	power_in	B-port supply rail. 1.65V ≤ VCCB ≤ 5.5V and must be ≥ VCCA. Sets the logic level for the B-side channels. Bypass locally with 0.1µF.
20	B1	bidirectional	B-port channel 1 I/O, referenced to VCCB. Paired with A1.

Key specifications

Parameter	Value
Type	8-bit bidirectional level translator
Direction	Automatic sensing (no DIR pin)
A-side supply (VCCA)	1.4-3.6 V
B-side supply (VCCB)	1.65-5.5 V
Channels	8
Output enable	OE pin (Hi-Z)
Package	TSSOP-20
Body (L×W×H)	6.5 × 4.4 × 1.2 mm

Ordering variants

Same part, different packaging or reel option.

TXS0108EPWR (TSSOP-20, tape & reel)

CAD (KiCad official)

Symbol: Logic_LevelTranslator:TXS0108EPW
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (45 pp, sha256 f41f9f58874399bb, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude) — every pin and dimension is cited to a datasheet page; refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF