component
TPS56628DDAR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPS56628DDAR
Texas Instruments · DC-DC Converters · SOIC-8-EP
TPS56628DDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable input control. Active high; must be pulled high to enable the converter. Internal ~400 kΩ pull-down to GND (200-800 kΩ). Absolute max −0.3 V to 20 V. |
| 2 | VFB | input | Converter feedback input. Connect to output voltage through a feedback resistor divider. Regulation threshold ≈ 0.765 V (typical). Absolute max −0.3 V to 6.5 V. |
| 3 | VREG5 | power_out | 5.5 V internal LDO regulator output used for internal bias. Requires a decoupling capacitor (typical 1 µF) to GND. Not active when EN is low. Output up to ~20 mA. |
| 4 | PG | output | Open-drain Power Good output. Asserts high (via external pull-up) when VFB rises above ~90% of nominal; deasserts below ~85%. Absolute max −0.3 V to 6.5 V; sink capability 2-4 mA. |
| 5 | GND | power_in | Ground pin. Power ground return for the switching circuit. Connect sensitive VFB return to GND at a single point. |
| 6 | SW | output | Switch node between the internal high-side and low-side NFETs. Connect to the output inductor. Absolute max −2 V to 20 V (−3 V to 22 V for 10 ns transient). |
| 7 | VBST | power_in | Bootstrap supply for the high-side FET gate driver. Connect a 0.1 µF capacitor from VBST to SW. An internal diode is connected between VREG5 and VBST. Absolute max −0.3 V to 26 V (−0.3 V to 6.5 V vs SW). |
| 8 | VIN | power_in | Input voltage supply pin. Operating range 4.5 V to 18 V; absolute max 20 V. Bypass locally with ceramic capacitance to GND. |
| 9 | PAD | power_in | Exposed thermal pad on the back side of the package. Must be soldered to the PCB ground plane to achieve adequate thermal dissipation. Must be connected to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8-EP |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
TPS56628DDAR
CAD (KiCad official)
- Symbol:
TPS56628DDAR - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
tps56628ddar-etched.step/tps56628ddar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps56628ddar.step/tps56628ddar.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
tps56628ddar.step |
125 KB | You want the bare part, or you mark your own boards. |
tps56628ddar-etched.step |
2.8 MB | You want the part with TPS56628DDAR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 659 faces against 152 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (25 pp, sha256
856a489d599d233c, retrieved 2026-08-17, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).