TM74HC595 from TM Shenzhen Titan Micro Elec, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	QB	tri_state	Parallel tri-state output B (bit 2 of the storage register). Drives up to IO = ±6.0 mA at VDD = 4.5 V (±7.8 mA at 6.0 V). Placed in high-impedance when /OE is high.
2	QC	tri_state	Parallel tri-state output C (bit 3 of the storage register). Same drive characteristics as QA-QH. High-impedance when /OE is high.
3	QD	tri_state	Parallel tri-state output D (bit 4 of the storage register). Same drive characteristics as QA-QH. High-impedance when /OE is high.
4	QE	tri_state	Parallel tri-state output E (bit 5 of the storage register). Same drive characteristics as QA-QH. High-impedance when /OE is high.
5	QF	tri_state	Parallel tri-state output F (bit 6 of the storage register). Same drive characteristics as QA-QH. High-impedance when /OE is high.
6	QG	tri_state	Parallel tri-state output G (bit 7 of the storage register). Same drive characteristics as QA-QH. High-impedance when /OE is high.
7	QH	tri_state	Parallel tri-state output H (bit 8, last stage of the storage register). Same drive characteristics as QA-QH. High-impedance when /OE is high.
8	GND	power_in	Ground (negative supply) reference for the device. Connect to system 0 V.
9	SQH	output	Serial data output - the shifted-out data from the last stage (QH) of the internal shift register. Used to cascade to the SI input of the next TM74HC595 for chains longer than 8 bits. Not tri-stated by /OE.
10	SCLR	input	Active-low shift-register clear (/SCLR). Driving this pin low asynchronously resets all stages of the shift register to 0; it does not affect the output storage latches until an RCK rising edge transfers the cleared data.
11	SCK	input	Shift-register clock input. Serial data on SI is sampled on the rising edge of SCK and shifted through the internal 8-bit shift register (SPI-compatible). Max frequency > 25 MHz.
12	RCK	input	Storage-register (latch) clock input. On the rising edge of RCK, the current contents of the shift register are transferred to the 8-bit output storage latches and appear on QA-QH (subject to /OE).
13	OE	input	Active-low output enable (/OE). When low, QA-QH drive the latched storage-register values; when high, QA-QH go to high impedance. Does not affect SQH or the shift-register contents.
14	SI	input	Serial data input. Data present on SI is clocked into the first stage of the shift register on the rising edge of SCK. Setup time tsu ≈ 3.0 ns (VDD=5.0 V), hold time th ≈ 2.0 ns.
15	QA	tri_state	Parallel tri-state output A (bit 1, first stage of the storage register). Drives up to IO = ±6.0 mA at VDD = 4.5 V (±7.8 mA at 6.0 V). High-impedance when /OE is high.
16	VCC	power_in	Positive supply input. Recommended operating range 2.0 V to 5.5 V. Quiescent current Icc ≈ 4 µA (max at 25 °C, 6 V).

Key specifications

Parameter	Value
Manufacturer	TM Shenzhen Titan Micro Elec
Package	SOP-16
Category	Logic
Pins	16

CAD (KiCad official)

Symbol: TM74HC595
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`tm74hc595.step`	217 KB	You want the bare part, or you mark your own boards.
`tm74hc595-etched.step`	2.1 MB	You want the part with `TM74HC595` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 546 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: TM Shenzhen Titan Micro Elec datasheet (8 pp, sha256 6212ea9b2c26f3b1, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF