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TLV9061IDBVR

Public Made by Adom

by adom

Texas Instruments Operational Amplifier, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentop-amp-cmptlv9061idbvr
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3D Model

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Datasheet

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Contents

README

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TLV9061IDBVR

Texas Instruments · Operational Amplifier · SOT-23-5

TLV9061IDBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT output Op-amp output. Rail-to-rail output swing, capable of driving up to ~100 pF of capacitive load with resistive open-loop output impedance easing stability with higher loads.
2 V- power_in Negative (low) supply rail, or ground for single-supply operation. Total supply voltage V+ minus V- must be 1.8 V to 5.5 V.
3 IN+ input Non-inverting analog input. Rail-to-rail common-mode input range; extremely low input bias current (~0.5 pA typ).
4 IN- input Inverting analog input. Rail-to-rail common-mode input range; extremely low input bias current (~0.5 pA typ).
5 V+ power_in Positive (high) supply rail. Total supply voltage V+ minus V- must be 1.8 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Op-amp/Cmp
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • TLV9061IDBVR
  • TLV9061IDBVT
  • TLV9061IDBVRIDRLR
  • TLV9061IDBVRIDRLT
  • TLV9061IDBVRIDCKR
  • TLV9061IDBVRIDCKT
  • TLV9061IDBVRIDPWR
  • TLV9061IDBVRIDPWT
  • TLV9061IDBVRIDR

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VOS -1.6 0.3 1.6 mV VS = 5 V 15
Input offset voltage VOS -2 2 mV VS = 5 V, TA = –40°C to 125°C 15
Offset voltage drift dVOS/dT -0.53 0.53 µV/°C VS = 5 V, TA = –40°C to 125°C 15
Power-supply rejection ratio PSRR -80 7 80 µV/V VS = 1.8 V – 5.5 V, VCM = (V–) 15
Common-mode rejection ratio CMRR 80 103 dB VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V, TA = –40°C to 125°C 15
Common-mode rejection ratio CMRR 57 87 dB VS = 5.5 V, VCM = –0.1 V to 5.6 V, TA = –40°C to 125°C 15
Common-mode rejection ratio CMRR 88 dB VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V, TA = –40°C to 125°C 15
Common-mode rejection ratio CMRR 81 dB VS = 1.8 V, VCM = –0.1 V to 1.9 V, TA = –40°C to 125°C 15
Input bias current IB -0.5 0.5 pA 15
Input offset current IOS -0.05 0.05 pA 15
Open-loop voltage gain AOL 100 dB VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V, RL = 10 kΩ 15
Open-loop voltage gain AOL 104 130 dB VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V, RL = 10 kΩ 15
Open-loop voltage gain AOL 130 dB VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V, RL = 2 kΩ 15
Voltage output swing from supply rails VO 20 mV VS = 5.5 V, RL = 10 kΩ 15
Voltage output swing from supply rails VO 60 mV VS = 5.5 V, RL = 2 kΩ 15
Short-circuit current ISC -50 50 mA VS = 5 V 15
Quiescent current per amplifier IQ 538 750 µA VS = 5.5 V, IO = 0 mA 16
Quiescent current per amplifier IQ 800 µA VS = 5.5 V, IO = 0 mA, TA = –40°C to 125°C 16
Supply voltage VS 1.8 5.5 V VS = (V+) – (V–) 12
Specified temperature TA -40 125 °C 12
Supply voltage [(V+) – (V–)] 0 6 V 12
Signal input pins current -10 10 mA Signal input pins (input current limit) 12
Specified temperature TA -40 125 °C 12
Junction temperature TJ 150 °C 12
Storage temperature Tstg -65 150 °C 12
Electrostatic discharge, human-body model V(ESD) -2500 2500 V HBM, ANSI/ESDA/JEDEC JS-001, TLV9061 packages 12
Electrostatic discharge, charged-device model V(ESD) -1500 1500 V CDM, JESD22-C101, TLV9061 packages 12
Junction-to-ambient thermal resistance RθJA 221.7 °C/W DBV (SOT-23), 5 pins 13
Junction-to-case (top) thermal resistance RθJC(top) 144.7 °C/W DBV (SOT-23), 5 pins 13
Junction-to-board thermal resistance RθJB 49.7 °C/W DBV (SOT-23), 5 pins 13
Junction-to-top characterization parameter ψJT 26.1 °C/W DBV (SOT-23), 5 pins 13
Junction-to-board characterization parameter ψJB 49 °C/W DBV (SOT-23), 5 pins 13

CAD (KiCad official)

  • Symbol: TLV9061IDBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tlv9061idbvr-etched.step / tlv9061idbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv9061idbvr.step / tlv9061idbvr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tlv9061idbvr.step 85 KB You want the bare part, or you mark your own boards.
tlv9061idbvr-etched.step 2.0 MB You want the part with TLV9061IDBVR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 492 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (75 pp, sha256 424562d65438d8ae, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF