TL084IDT
Public Made by Adomby adom
STMicroelectronics FET InputAmplifiers, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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markdownTL084IDT
STMicroelectronics · FET InputAmplifiers · SOIC-14
TL084IDT from STMicroelectronics, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT1 | output | Amplifier 1 output. |
| 2 | IN1- | input | Amplifier 1 inverting input (JFET gate, very high input impedance). |
| 3 | IN1+ | input | Amplifier 1 non-inverting input (JFET gate, very high input impedance). |
| 4 | VCC+ | power_in | Positive supply. Total supply range 6 V to 36 V (±3 V to ±18 V), absolute max ±18 V. |
| 5 | IN2+ | input | Amplifier 2 non-inverting input (JFET gate, very high input impedance). |
| 6 | IN2- | input | Amplifier 2 inverting input (JFET gate, very high input impedance). |
| 7 | OUT2 | output | Amplifier 2 output. |
| 8 | OUT3 | output | Amplifier 3 output. |
| 9 | IN3- | input | Amplifier 3 inverting input (JFET gate, very high input impedance). |
| 10 | IN3+ | input | Amplifier 3 non-inverting input (JFET gate, very high input impedance). |
| 11 | VCC- | power_in | Negative supply (or GND in single-supply operation). Absolute max ±18 V with respect to VCC+ midpoint. |
| 12 | IN4+ | input | Amplifier 4 non-inverting input (JFET gate, very high input impedance). |
| 13 | IN4- | input | Amplifier 4 inverting input (JFET gate, very high input impedance). |
| 14 | OUT4 | output | Amplifier 4 output. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-14 |
| Category | Op-amp/Cmp |
| Pins | 14 |
Ordering variants
Same part, different packaging or reel option.
TL084IDTTL084IDTCDTTL084IDTCDTL084IDTACDTTL084IDTACDTL084IDTBCDTTL084IDTBCDTL084IDTAIDTTL084IDTAIDTL084IDTBIDTTL084IDTBIDTL084IDTNTL084IDTINTL084IDTCNTL084IDTACNTL084IDTBCNTL084IDTAINTL084IDTBINTL084IDTPTTL084IDTIPTTL084IDTCPTTL084IDTACPTTL084IDTBCPTTL084IDTAIPTTL084IDTBIPT
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input offset voltage (Rs = 50 Ω), Tamb = +25 °C, TL084 | Vio | 3 | 10 | mV | Rs = 50 Ω; Tamb = +25 °C; TL084 | 6 | |
| Input offset voltage (Rs = 50 Ω), Tmin ≤ Tamb ≤ Tmax, TL084 | Vio | 13 | mV | Rs = 50 Ω; Tmin ≤ Tamb ≤ Tmax; TL084 | 6 | ||
| Input offset current, Tamb = +25 °C | Iio | 5 | 100 | pA | Tamb = +25 °C | 6 | |
| Input offset current, Tmin ≤ Tamb ≤ Tmax | Iio | 4 | nA | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Input bias current, Tamb = +25 °C | Iib | 20 | 200 | pA | Tamb = +25 °C | 6 | |
| Input bias current, Tmin ≤ Tamb ≤ Tmax | Iib | 20 | nA | Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Large signal voltage gain, Tamb = +25 °C | Avd | 50 | 200 | V/mV | RL = 2 kΩ, Vo = ±10 V; Tamb = +25 °C | 6 | |
| Large signal voltage gain, Tmin ≤ Tamb ≤ Tmax | Avd | 25 | V/mV | RL = 2 kΩ, Vo = ±10 V; Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Supply voltage rejection ratio, Tamb = +25 °C | SVR | 80 | 86 | dB | RS = 50 Ω; Tamb = +25 °C | 6 | |
| Supply voltage rejection ratio, Tmin ≤ Tamb ≤ Tmax | SVR | 80 | dB | RS = 50 Ω; Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Supply current, no load, Tamb = +25 °C | ICC | 1.4 | 2.5 | mA | No load; Tamb = +25 °C | 6 | |
| Supply current, no load, Tmin ≤ Tamb ≤ Tmax | ICC | 2.5 | mA | No load; Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Input common mode voltage range | Vicm | -12 | 15 | V | 6 | ||
| Common mode rejection ratio, Tamb = +25 °C | CMR | 80 | 86 | dB | RS = 50 Ω; Tamb = +25 °C | 6 | |
| Common mode rejection ratio, Tmin ≤ Tamb ≤ Tmax | CMR | 80 | dB | RS = 50 Ω; Tmin ≤ Tamb ≤ Tmax | 6 | ||
| Output short-circuit current, Tamb = +25 °C | Ios | 10 | 40 | mA | Tamb = +25 °C | 6 | |
| Output short-circuit current, Tmin ≤ Tamb ≤ Tmax | Ios | 10 | 60 | mA | Tmin ≤ Tamb ≤ Tmax | 6 | |
| Output voltage swing, RL = 2 kΩ, Tamb = +25 °C | ±Vopp | 10 | V | Tamb = +25 °C; RL = 2 kΩ | 6 | ||
| Output voltage swing, RL = 10 kΩ, Tamb = +25 °C | ±Vopp | 12 | V | Tamb = +25 °C; RL = 10 kΩ | 6 | ||
| Output voltage swing, RL = 2 kΩ, Tmin ≤ Tamb ≤ Tmax | ±Vopp | 10 | V | Tmin ≤ Tamb ≤ Tmax; RL = 2 kΩ | 6 | ||
| Output voltage swing, RL = 10 kΩ, Tmin ≤ Tamb ≤ Tmax | ±Vopp | 12 | V | Tmin ≤ Tamb ≤ Tmax; RL = 10 kΩ | 6 | ||
| Slew rate | SR | 8 | 16 | V/μs | Vin = 10 V, RL = 2 kΩ, CL = 100 pF, unity gain | 6 | |
| Gain bandwidth product | GBP | 2.5 | 4 | MHz | Vin = 10 mV, RL = 2 kΩ, CL = 100 pF, F = 100 kHz | 6 | |
| Phase margin | ∅m | 45 | degree | 6 | |||
| Channel separation | Vo1/Vo2 | 120 | dB | Av = 100 | 7 | ||
| Supply voltage | VCC | -18 | 18 | V | Voltages referenced to supply midpoint | 4 | |
| Input voltage | Vin | -15 | 15 | V | Must not exceed supply magnitude or 15 V, whichever is less | 4 | |
| Differential input voltage | Vid | -30 | 30 | V | 4 | ||
| Power dissipation | Ptot | 680 | mW | 4 | |||
| ESD human body model | HBM | 1000 | V | 100 pF discharged through 1.5 kΩ | 4 | ||
| ESD machine model | MM | 150 | V | 200 pF, no series resistor | 4 | ||
| ESD charged device model | CDM | 1500 | V | All pins plus package charged together | 4 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 4 | ||
| Operating free-air temperature range, TL084I/AI/BI | Toper | -40 | 105 | °C | TL084I/AI/BI grade | 4 | |
| Thermal resistance junction to ambient, SO-14 | Rthja | 105 | °C/W | Typical value | 4 | ||
| Thermal resistance junction to case, SO-14 | Rthjc | 31 | °C/W | Typical value | 4 | ||
| Supply voltage range | VCC | 6 | 36 | V | 5 | ||
| Operating free-air temperature range, TL084I/AI/BI | Toper | -40 | 105 | °C | TL084I/AI/BI grade | 5 |
CAD (KiCad official)
- Symbol:
TL084IDT - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
tl084idt-etched.step/tl084idt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tl084idt.step/tl084idt.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
tl084idt.step |
195 KB | You want the bare part, or you mark your own boards. |
tl084idt-etched.step |
1.8 MB | You want the part with TL084IDT already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 477 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (19 pp, sha256
e20abb69cf237782, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).