TEA1995T from NXP Semicon, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GDB	output	Gate drive output for external SR MOSFET B. Source/sink capable driver; output voltage limited to VG(max) (typically ~11 V from internal driver supply; limited to VCC when VCC = 5 V for logic-level MOSFETs). Actively pulled low during UVLO and start-up.
2	GND	power_in	Device ground reference. The VCC decoupling capacitor must be connected between VCC and GND as close as possible to the IC to minimize inductance from high gate driver currents.
3	DSB	input	Drain sense input for synchronous timing of MOSFET B. Handles input voltages up to 100 V. Positive drain sense voltages hold the gate driver off; negative voltages (differential vs SSB) enable SR conduction.
4	SSB	input	Source sense (Kelvin) input for MOSFET B. Must be connected as close as possible to the source pin of the external SR MOSFET to minimize measurement errors from PCB trace parasitic inductance under high dI/dt.
5	SSA	input	Source sense (Kelvin) input for MOSFET A. Must be connected as close as possible to the source pin of the external SR MOSFET to minimize measurement errors from PCB trace parasitic inductance under high dI/dt.
6	DSA	input	Drain sense input for synchronous timing of MOSFET A. Handles input voltages up to 100 V. Positive drain sense voltages hold the gate driver off; negative voltages (differential vs SSA) enable SR conduction.
7	VCC	power_in	Supply voltage input. Operates over 4.5 V to 38 V. UVLO releases above Vstart and re-engages below Vstop. Must be decoupled with a dedicated capacitor between VCC and GND placed close to the IC.
8	GDA	output	Gate drive output for external SR MOSFET A. Source/sink capable driver; output voltage limited to VG(max) (typically ~11 V from internal driver supply; limited to VCC when VCC = 5 V for logic-level MOSFETs). Actively pulled low during UVLO and start-up.

Key specifications

Parameter	Value
Manufacturer	NXP Semicon
Package	SO-8
Category	PMIC
Pins	8

Ordering variants

Same part, different packaging or reel option.

TEA1995T/1

CAD (KiCad official)

Symbol: TEA1995T
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SO-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`tea1995t.step`	122 KB	You want the bare part, or you mark your own boards.
`tea1995t-etched.step`	1.6 MB	You want the part with `TEA1995T` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 402 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: NXP Semicon datasheet (18 pp, sha256 c53015a654fe5b12, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF