STPIC6C595MTR from STMicroelectronics, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC	power_in	Logic supply voltage. Recommended 4.5 V to 5.5 V (absolute max 7 V).
2	SER IN	input	Serial data input to the 8-bit shift register. Sampled on the rising edge of SRCK. Setup time 1.6 ns min / 3 ns typ before SRCK rising edge.
3	DRAIN0	output	Open-drain DMOS output 0. Sinks up to 100 mA continuous / 250 mA peak with a 33 V clamp. Off when the corresponding storage-register bit is low or when /G is high.
4	DRAIN1	output	Open-drain DMOS output 1. Sinks up to 100 mA continuous / 250 mA peak with a 33 V clamp.
5	DRAIN2	output	Open-drain DMOS output 2. Sinks up to 100 mA continuous / 250 mA peak with a 33 V clamp.
6	DRAIN3	output	Open-drain DMOS output 3. Sinks up to 100 mA continuous / 250 mA peak with a 33 V clamp.
7	/CLR	input	Active-low shift-register clear. When low the input shift register is cleared; when high normal operation. Does not affect the storage register directly.
8	/G	input	Active-low output enable. When high all DMOS drain outputs are forced off (data in output buffer held low); when low data from the storage register drives the outputs.
9	SER OUT	output	Serial data output from the last stage of the shift register. Used to cascade multiple STPIC6C595 devices.
10	RCK	input	Register (storage) clock. Rising edge transfers shift-register contents into the 8-bit D-type storage register whose outputs drive the DMOS buffers.
11	DRAIN4	output	Open-drain DMOS output 4. Sinks up to 100 mA continuous / 250 mA peak with a 33 V clamp.
12	DRAIN5	output	Open-drain DMOS output 5. Sinks up to 100 mA continuous / 250 mA peak with a 33 V clamp.
13	DRAIN6	output	Open-drain DMOS output 6. Sinks up to 100 mA continuous / 250 mA peak with a 33 V clamp.
14	DRAIN7	output	Open-drain DMOS output 7. Sinks up to 100 mA continuous / 250 mA peak with a 33 V clamp.
15	SRCK	input	Shift-register clock. Rising edge clocks SER IN data into the shift register and shifts existing contents toward SER OUT.
16	GND	power_in	Ground reference for logic and DMOS source pins.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SO-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

STPIC6C595MTR
STPIC6C595MTRTTR

CAD (KiCad official)

Symbol: STPIC6C595MTR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SO-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`stpic6c595mtr.step`	217 KB	You want the bare part, or you mark your own boards.
`stpic6c595mtr-etched.step`	3.1 MB	You want the part with `STPIC6C595MTR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 754 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (22 pp, sha256 eeea45d02275800c, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF