STM8S103K3T6CTR from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NRST	bidirectional	Active-low device reset input/open-drain output with internal pull-up. Drive low to reset the MCU; released by internal watchdog/POR events.
2	PA1/OSCIN	bidirectional	Port A1 GPIO; alternate function: external crystal/resonator input (OSCIN) for the HSE oscillator. In Halt/Active-halt PA1 is forced to input weak pull-up and cannot wake the device.
3	PA2/OSCOUT	bidirectional	Port A2 GPIO; alternate function: crystal/resonator output (OSCOUT) driving the HSE oscillator.
4	VSS	power_in	Digital ground reference for the MCU core and I/Os.
5	VCAP	passive	1.8 V internal regulator decoupling capacitor pin. Connect a ceramic cap (typically 1 uF) to VSS; do not power externally.
6	VDD	power_in	Digital power supply, 2.95 V to 5.5 V. Decouple to VSS.
7	PA3/TIM2_CH3[SPI_NSS]	bidirectional	Port A3 high-sink GPIO; default alternate: TIM2 capture/compare channel 3; after AFR1 remap: SPI slave-select (NSS).
8	PF4	bidirectional	Port F4 general-purpose I/O (standard drive, no alternate function on this pin).
9	PB7	bidirectional	Port B7 high-sink GPIO (no assigned alternate function).
10	PB6	bidirectional	Port B6 high-sink GPIO (no assigned alternate function).
11	PB5/I2C_SDA	bidirectional	Port B5 (true open-drain) / I2C data (SDA). External pull-up required for I2C use; supports up to 400 kbit/s.
12	PB4/I2C_SCL	bidirectional	Port B4 (true open-drain) / I2C clock (SCL). External pull-up required for I2C use.
13	PB3/AIN3/TIM1_ETR	bidirectional	Port B3 high-sink GPIO; ADC1 analog input channel 3 (AIN3); TIM1 external trigger (ETR).
14	PB2/AIN2/TIM1_CH3N	bidirectional	Port B2 high-sink GPIO; ADC1 analog input channel 2 (AIN2); TIM1 inverted complementary output channel 3 (CH3N).
15	PB1/AIN1/TIM1_CH2N	bidirectional	Port B1 high-sink GPIO; ADC1 analog input channel 1 (AIN1); TIM1 inverted complementary output channel 2 (CH2N).
16	PB0/AIN0/TIM1_CH1N	bidirectional	Port B0 high-sink GPIO; ADC1 analog input channel 0 (AIN0); TIM1 inverted complementary output channel 1 (CH1N).
17	PE5/SPI_NSS	bidirectional	Port E5 high-sink GPIO; SPI slave-select (NSS) master/slave select line.
18	PC1/TIM1_CH1/UART1_CK	bidirectional	Port C1 high-sink GPIO; TIM1 capture/compare channel 1 (CH1); UART1 synchronous clock output (CK).
19	PC2/TIM1_CH2	bidirectional	Port C2 high-sink GPIO; TIM1 capture/compare channel 2 (CH2).
20	PC3/TIM1_CH3	bidirectional	Port C3 high-sink GPIO; TIM1 capture/compare channel 3 (CH3).
21	PC4/TIM1_CH4/CLK_CCO	bidirectional	Port C4 high-sink GPIO; TIM1 capture/compare channel 4 (CH4); default alternate configurable clock output (CLK_CCO).
22	PC5/SPI_SCK	bidirectional	Port C5 high-sink GPIO; SPI clock (SCK), up to 8 Mbit/s.
23	PC6/SPI_MOSI	bidirectional	Port C6 high-sink GPIO; SPI MOSI (master-out/slave-in) data line.
24	PC7/SPI_MISO	bidirectional	Port C7 high-sink GPIO; SPI MISO (master-in/slave-out) data line.
25	PD0/TIM1_BKIN[CLK_CCO]	bidirectional	Port D0 high-sink GPIO; default alternate TIM1 break input (BKIN); after AFR5 remap: configurable clock output (CLK_CCO).
26	PD1/SWIM	bidirectional	Port D1 high-sink GPIO; SWIM single-wire interface data line for debug and programming. PD1 is in input pull-up during reset phase and after internal reset release.
27	PD2[TIM2_CH3]	bidirectional	Port D2 high-sink GPIO; after AFR1 remap: TIM2 capture/compare channel 3.
28	PD3/TIM2_CH2/ADC_ETR	bidirectional	Port D3 high-sink GPIO; TIM2 capture/compare channel 2; ADC external trigger (ADC_ETR).
29	PD4/BEEP/TIM2_CH1	bidirectional	Port D4 high-sink GPIO; TIM2 capture/compare channel 1; BEEP output (beeper).
30	PD5/UART1_TX	bidirectional	Port D5 high-sink GPIO; UART1 data transmit (TX).
31	PD6/UART1_RX	bidirectional	Port D6 high-sink GPIO; UART1 data receive (RX).
32	PD7/TLI[TIM1_CH4]	bidirectional	Port D7 high-sink GPIO; default alternate top-level interrupt (TLI); after AFR6 remap: TIM1 capture/compare channel 4.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-32(7x7)
Category	MCU
Pins	32

Ordering variants

Same part, different packaging or reel option.

STM8S103K3T6CTR
STM8S103K3T6CTRT3CTR
STM8S103K3T6CTRU6TR
STM8S103K3T6CTRU6
STM8S103K3T6CTRU3TR
STM8S103K3T6CTRB6
STM8S103K3T6CTRB3
STM8S103K3T6CTRP6
STM8S103K3T6CTRP3
STM8S103K3T6CTRM6
STM8S103K3T6CTRM3
STM8S103K3T6CTRU3

CAD (KiCad official)

Symbol: STM8S103K3T6CTR
Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
3D model: LQFP-32(7x7) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`stm8s103k3t6ctr.step`	413 KB	You want the bare part, or you mark your own boards.
`stm8s103k3t6ctr-etched.step`	4.4 MB	You want the part with `STM8S103K3T6CTR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1088 faces against 507 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (121 pp, sha256 ac23789ac0a2f408, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF