STM8S003K3T6CTR from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NRST	bidirectional	Active-low bidirectional reset. Internal weak pull-up; asserted low during external or internal reset. Connect a decoupling capacitor to VSS per NRST characteristics.
2	PA1/OSCIN	bidirectional	Port A1 GPIO / HSE crystal-resonator input (OSCIN). Standard I/O, slow (O1), open-drain or push-pull. Reset default: floating input. In Halt/Active-halt PA1 is auto-configured as weak pull-up input and cannot wake the device; use as input only in those modes.
3	PA2/OSCOUT	bidirectional	Port A2 GPIO / HSE crystal-resonator output (OSCOUT). Standard I/O, slow (O1). Reset default: floating input.
4	VSS	power_in	Digital ground reference for the MCU.
5	VCAP	passive	1.8 V internal LDO regulator output. Requires an external decoupling capacitor to VSS (see VCAP external capacitor spec). Do not power externally.
6	VDD	power_in	Digital power supply, 2.95 V to 5.5 V operating range.
7	PA3/TIM2_CH3/[SPI_NSS]	bidirectional	Port A3 high-sink GPIO. Default alternate: TIM2 channel 3. Remap alternate (AFR1 option bit): SPI master/slave select (NSS).
8	PF4	bidirectional	Port F4 general-purpose I/O, standard (non high-sink), slow (O1).
9	PB7	bidirectional	Port B7 general-purpose I/O, standard, slow (O1).
10	PB6	bidirectional	Port B6 general-purpose I/O, standard, slow (O1).
11	PB5/I2C_SDA	bidirectional	Port B5 / I2C data line. True open-drain output (no internal pull-up, no protection diode to VDD); requires external pull-up. Supports I2C up to 400 kbit/s.
12	PB4/I2C_SCL	bidirectional	Port B4 / I2C clock line. True open-drain output (no internal pull-up, no protection diode to VDD); requires external pull-up.
13	PB3/AIN3/[TIM1_ETR]	bidirectional	Port B3 high-sink GPIO. Alternates: ADC analog input AIN3 (channel 3); TIM1 external trigger (TIM1_ETR) via remap.
14	PB2/AIN2/[TIM1_CH3N]	bidirectional	Port B2 high-sink GPIO. Alternates: ADC AIN2; TIM1 inverted channel 3 (TIM1_CH3N) via remap.
15	PB1/AIN1/[TIM1_CH2N]	bidirectional	Port B1 high-sink GPIO. Alternates: ADC AIN1; TIM1 inverted channel 2 (TIM1_CH2N) via remap.
16	PB0/AIN0/[TIM1_CH1N]	bidirectional	Port B0 high-sink GPIO. Alternates: ADC AIN0; TIM1 inverted channel 1 (TIM1_CH1N) via remap.
17	PE5/SPI_NSS	bidirectional	Port E5 high-sink GPIO / SPI master or slave select (NSS).
18	PC1/TIM1_CH1/UART1_CK	bidirectional	Port C1 high-sink GPIO. Alternates: TIM1 channel 1; UART1 synchronous clock output (UART1_CK).
19	PC2/TIM1_CH2	bidirectional	Port C2 high-sink GPIO. Alternate: TIM1 channel 2.
20	PC3/TIM1_CH3	bidirectional	Port C3 high-sink GPIO. Alternate: TIM1 channel 3.
21	PC4/TIM1_CH4/CLK_CCO	bidirectional	Port C4 high-sink GPIO. Alternates: TIM1 channel 4; configurable clock output (CLK_CCO).
22	PC5/SPI_SCK	bidirectional	Port C5 high-sink GPIO / SPI clock (SCK). SPI runs up to 8 Mbit/s.
23	PC6/SPI_MOSI	bidirectional	Port C6 high-sink GPIO / SPI master-out / slave-in data (MOSI).
24	PC7/SPI_MISO	bidirectional	Port C7 high-sink GPIO / SPI master-in / slave-out data (MISO).
25	PD0/TIM1_BKIN/[CLK_CCO]	bidirectional	Port D0 high-sink GPIO. Default alternate: TIM1 break input (TIM1_BKIN). Remap alternate (AFR5): configurable clock output (CLK_CCO).
26	PD1/SWIM	bidirectional	Port D1 high-sink GPIO / SWIM single-wire debug and programming interface. Reset state is input pull-up during and after reset release.
27	PD2/[TIM2_CH3]	bidirectional	Port D2 high-sink GPIO. Remap alternate (AFR1): TIM2 channel 3.
28	PD3/TIM2_CH2/[ADC_ETR]	bidirectional	Port D3 high-sink GPIO. Alternates: TIM2 channel 2; ADC external trigger (ADC_ETR).
29	PD4/BEEP/TIM2_CH1	bidirectional	Port D4 high-sink GPIO. Alternates: TIM2 channel 1; BEEP output.
30	PD5/UART1_TX	bidirectional	Port D5 high-sink GPIO / UART1 transmit data (TX).
31	PD6/UART1_RX	bidirectional	Port D6 high-sink GPIO / UART1 receive data (RX).
32	PD7/TLI/[TIM1_CH4]	bidirectional	Port D7 high-sink GPIO. Default alternate: TLI top-level (non-maskable) interrupt input. Remap alternate (AFR6): TIM1 channel 4.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-32(7x7)
Category	MCU
Pins	32

Ordering variants

Same part, different packaging or reel option.

STM8S003K3T6CTR
STM8S003K3T6TR
STM8S003K3T6CTRF3P6
STM8S003K3T6CTRF3U6

CAD (KiCad official)

Symbol: STM8S003K3T6CTR
Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
3D model: LQFP-32(7x7) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`stm8s003k3t6ctr.step`	413 KB	You want the bare part, or you mark your own boards.
`stm8s003k3t6ctr-etched.step`	4.6 MB	You want the part with `STM8S003K3T6CTR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1118 faces against 507 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (104 pp, sha256 f22af8c2e2680b97, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF