STM32L151RET6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VLCD	power_in	LCD external voltage input. On STM32L151xE (no LCD), this pin should be connected to VDD.
2	PC13-WKUP2	bidirectional	GPIO PC13, also wake-up 2 / RTC_TAMP1 / RTC_TS / RTC_OUT additional functions.
3	PC14-OSC32_IN	bidirectional	LSE 32 kHz crystal input when LSEON=1; otherwise general-purpose PH0/PC14 GPIO. LSE has priority over GPIO.
4	PC15-OSC32_OUT	bidirectional	LSE 32 kHz crystal output when LSEON=1; otherwise GPIO PC15.
5	PH0-OSC_IN	bidirectional	HSE crystal/clock input when HSEON=1, otherwise GPIO PH0. HSE has priority over GPIO.
6	PH1-OSC_OUT	bidirectional	HSE crystal output when HSEON=1, otherwise GPIO PH1.
7	NRST	bidirectional	Bidirectional device reset input/open-drain output with embedded weak pull-up. Active low.
8	PC0	bidirectional	GPIO PC0. Alt: LCD_SEG18. Additional: ADC_IN10 / COMP1_INP.
9	PC1	bidirectional	GPIO PC1. Alt: LCD_SEG19. Additional: ADC_IN11 / COMP1_INP.
10	PC2	bidirectional	GPIO PC2. Alt: LCD_SEG20. Additional: ADC_IN12 / COMP1_INP.
11	PC3	bidirectional	GPIO PC3. Alt: LCD_SEG21. Additional: ADC_IN13 / COMP1_INP.
12	VSSA	power_in	Analog ground reference for ADC, DAC, reset block, RCs and PLL.
13	VDDA	power_in	Analog power supply (1.65-3.6 V) for ADC, DAC, reset block, RCs, and PLL.
14	PA0-WKUP1	bidirectional	GPIO PA0. Alt: TIM2_CH1_ETR / TIM5_CH1 / USART2_CTS. Additional: WKUP1/RTC_TAMP2/ADC_IN0/COMP1_INP.
15	PA1	bidirectional	GPIO PA1. Alt: TIM2_CH2 / TIM5_CH2 / USART2_RTS / LCD_SEG0. Additional: ADC_IN1 / COMP1_INP / OPAMP1_VINP.
16	PA2	bidirectional	GPIO PA2. Alt: TIM2_CH3 / TIM5_CH3 / TIM9_CH1 / USART2_TX / LCD_SEG1. Additional: ADC_IN2 / COMP1_INP / OPAMP1_VINM.
17	PA3	bidirectional	GPIO PA3. Alt: TIM2_CH4 / TIM5_CH4 / TIM9_CH2 / USART2_RX / LCD_SEG2. Additional: ADC_IN3 / COMP1_INP / OPAMP1_VOUT.
18	VSS_4	power_in	Ground reference for digital core (VSS domain 4).
19	VDD_4	power_in	Digital core power supply, 1.65-3.6 V (VDD domain 4).
20	PA4	bidirectional	GPIO PA4. Alt: SPI1_NSS / SPI3_NSS / I2S3_WS / USART2_CK. Additional: ADC_IN4 / DAC_OUT1 / COMP1_INP.
21	PA5	bidirectional	GPIO PA5. Alt: TIM2_CH1_ETR / SPI1_SCK. Additional: ADC_IN5 / DAC_OUT2 / COMP1_INP.
22	PA6	bidirectional	GPIO PA6. Alt: TIM3_CH1 / TIM10_CH1 / SPI1_MISO / LCD_SEG3. Additional: ADC_IN6 / COMP1_INP / OPAMP2_VINP.
23	PA7	bidirectional	GPIO PA7. Alt: TIM3_CH2 / TIM11_CH1 / SPI1_MOSI / LCD_SEG4. Additional: ADC_IN7 / COMP1_INP / OPAMP2_VINM.
24	PC4	bidirectional	GPIO PC4. Alt: LCD_SEG22. Additional: ADC_IN14 / COMP1_INP.
25	PC5	bidirectional	GPIO PC5. Alt: LCD_SEG23. Additional: ADC_IN15 / COMP1_INP.
26	PB0	bidirectional	GPIO PB0. Alt: TIM3_CH3 / LCD_SEG5. Additional: ADC_IN8 / COMP1_INP / OPAMP2_VOUT / VREF_OUT.
27	PB1	bidirectional	GPIO PB1. Alt: TIM3_CH4 / LCD_SEG6. Additional: ADC_IN9 / COMP1_INP / VREF_OUT.
28	PB2/BOOT1	bidirectional	GPIO PB2 doubling as BOOT1 latch during reset (selects boot memory area with BOOT0). Additional: ADC_IN0b.
29	PB10	bidirectional	GPIO PB10. Alt: TIM2_CH3 / I2C2_SCL / USART3_TX / LCD_SEG10.
30	PB11	bidirectional	GPIO PB11. Alt: TIM2_CH4 / I2C2_SDA / USART3_RX / LCD_SEG11.
31	VSS_1	power_in	Ground reference for digital core (VSS domain 1).
32	VDD_1	power_in	Digital core power supply, 1.65-3.6 V (VDD domain 1).
33	PB12	bidirectional	GPIO PB12. Alt: TIM10_CH1 / I2C2_SMBA / SPI2_NSS / I2S2_WS / USART3_CK / LCD_SEG12. Additional: ADC_IN18 / COMP1_INP.
34	PB13	bidirectional	GPIO PB13. Alt: TIM9_CH1 / SPI2_SCK / I2S2_CK / USART3_CTS / LCD_SEG13. Additional: ADC_IN19 / COMP1_INP.
35	PB14	bidirectional	GPIO PB14. Alt: TIM9_CH2 / SPI2_MISO / USART3_RTS / LCD_SEG14. Additional: ADC_IN20 / COMP1_INP.
36	PB15	bidirectional	GPIO PB15. Alt: TIM11_CH1 / SPI2_MOSI / I2S2_SD / LCD_SEG15. Additional: ADC_IN21 / COMP1_INP / RTC_REFIN.
37	PC6	bidirectional	GPIO PC6. Alt: TIM3_CH1 / I2S2_MCK / LCD_SEG24.
38	PC7	bidirectional	GPIO PC7. Alt: TIM3_CH2 / I2S3_MCK / LCD_SEG25.
39	PC8	bidirectional	GPIO PC8. Alt: TIM3_CH3 / LCD_SEG26.
40	PC9	bidirectional	GPIO PC9. Alt: TIM3_CH4 / LCD_SEG27.
41	PA8	bidirectional	GPIO PA8. Alt: USART1_CK / MCO / LCD_COM0.
42	PA9	bidirectional	GPIO PA9. Alt: USART1_TX / LCD_COM1.
43	PA10	bidirectional	GPIO PA10. Alt: USART1_RX / LCD_COM2.
44	PA11	bidirectional	GPIO PA11. Alt: USART1_CTS / SPI1_MISO. Additional: USB_DM (USB 2.0 FS D-).
45	PA12	bidirectional	GPIO PA12. Alt: USART1_RTS / SPI1_MOSI. Additional: USB_DP (USB 2.0 FS D+).
46	PA13/JTMS-SWDIO	bidirectional	GPIO PA13; default after reset is JTMS-SWDIO serial-wire debug data.
47	VSS_2	power_in	Ground reference for digital core (VSS domain 2).
48	VDD_2	power_in	Digital core power supply, 1.65-3.6 V (VDD domain 2).
49	PA14/JTCK-SWCLK	bidirectional	GPIO PA14; default after reset is JTCK-SWCLK serial-wire/JTAG clock.
50	PA15/JTDI	bidirectional	GPIO PA15; default after reset is JTDI JTAG data-in. Alt: TIM2_CH1_ETR / SPI1_NSS / SPI3_NSS / I2S3_WS / LCD_SEG17 / JTDI.
51	PC10	bidirectional	GPIO PC10. Alt: SPI3_SCK / I2S3_CK / USART3_TX / UART4_TX / LCD_SEG28 / LCD_SEG40 / LCD_COM4.
52	PC11	bidirectional	GPIO PC11. Alt: SPI3_MISO / USART3_RX / UART4_RX / LCD_SEG29 / LCD_SEG41 / LCD_COM5.
53	PC12	bidirectional	GPIO PC12. Alt: SPI3_MOSI / I2S3_SD / USART3_CK / UART5_TX / LCD_SEG30 / LCD_SEG42 / LCD_COM6.
54	PD2	bidirectional	GPIO PD2. Alt: TIM3_ETR / UART5_RX / LCD_SEG31 / LCD_SEG43 / LCD_COM7.
55	PB3/JTDO	bidirectional	GPIO PB3; default after reset is JTDO JTAG data-out. Alt: TIM2_CH2 / SPI1_SCK / SPI3_SCK / I2S3_CK / LCD_SEG7 / JTDO. Additional: COMP2_INM.
56	PB4/NJTRST	bidirectional	GPIO PB4; default after reset is NJTRST JTAG reset (active low). Alt: TIM3_CH1 / SPI1_MISO / SPI3_MISO / LCD_SEG8 / NJTRST. Additional: COMP2_INP.
57	PB5	bidirectional	GPIO PB5. Alt: TIM3_CH2 / I2C1_SMBA / SPI1_MOSI / SPI3_MOSI / I2S3_SD / LCD_SEG9. Additional: COMP2_INP.
58	PB6	bidirectional	GPIO PB6. Alt: TIM4_CH1 / I2C1_SCL / USART1_TX. Additional: COMP2_INP.
59	PB7	bidirectional	GPIO PB7. Alt: TIM4_CH2 / I2C1_SDA / USART1_RX. Additional: COMP2_INP / PVD_IN.
60	BOOT0	input	Boot memory select input, latched with BOOT1(PB2) at reset to choose Main Flash, System memory (bootloader), or SRAM as boot area.
61	PB8	bidirectional	GPIO PB8. Alt: TIM4_CH3 / TIM10_CH1 / I2C1_SCL / LCD_SEG16.
62	PB9	bidirectional	GPIO PB9. Alt: TIM4_CH4 / TIM11_CH1 / I2C1_SDA / LCD_COM3.
63	VSS_3	power_in	Ground reference for digital core (VSS domain 3).
64	VDD_3	power_in	Digital core power supply, 1.65-3.6 V (VDD domain 3).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-64(10x10)
Category	MCU
Pins	64

Ordering variants

Same part, different packaging or reel option.

STM32L151RET6
STM32L151RET6TR
STM32L151RET6RET7
STM32L151RET6RET7TR
STM32L151RET6VET6
STM32L151RET6VET6TR
STM32L151RET6VET7
STM32L151RET6VET7TR
STM32L151RET6ZET6
STM32L151RET6ZET6TR
STM32L151RET6ZET7
STM32L151RET6ZET7TR
STM32L151RET6QEH6
STM32L151RET6QEH6TR
STM32L151RET6UE

CAD (KiCad official)

Symbol: STM32L151RET6
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`stm32l151ret6.step`	847 KB	You want the bare part, or you mark your own boards.
`stm32l151ret6-etched.step`	5.3 MB	You want the part with `STM32L151RET6` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1342 faces against 995 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (136 pp, sha256 0d2f673e0c6974fa, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF