STM32L151CBT6A from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VLCD	power_in	LCD driver rail input. STM32L151 devices have no LCD controller; tie this pin to VDD per note 3 in Table 9.
2	PC13-WKUP2	bidirectional	General-purpose I/O port C bit 13. Additional functions: RTC_TAMP1/RTC_TS/RTC_OUT/WKUP2 low-power wake-up input. 5 V-tolerant FT I/O.
3	PC14-OSC32_IN	bidirectional	General-purpose I/O port C bit 14 or LSE 32.768 kHz crystal input (OSC32_IN) when LSE oscillator is enabled. Standard 3.3 V TC I/O.
4	PC15-OSC32_OUT	bidirectional	General-purpose I/O port C bit 15 or LSE 32.768 kHz crystal output (OSC32_OUT) when LSE oscillator is enabled. Standard 3.3 V TC I/O.
5	PH0-OSC_IN	bidirectional	General-purpose I/O port H bit 0 or HSE crystal input (OSC_IN) when HSE oscillator is enabled. Standard 3.3 V TC I/O.
6	PH1-OSC_OUT	bidirectional	General-purpose I/O port H bit 1 or HSE crystal output (OSC_OUT) when HSE oscillator is enabled. Standard 3.3 V TC I/O.
7	NRST	bidirectional	Bidirectional device reset input/open-drain output with internal weak pull-up (~40 k). Drive low for at least tNRST to force a system reset.
8	VSSA	power_in	Analog ground reference for the ADC, DAC, comparators and internal reference voltage. Tie to system ground through a low-impedance path.
9	VDDA	power_in	Analog supply for the ADC, DAC, reset block, PLL, comparators and internal reference voltage. Operating range 1.8-3.6 V (down to 1.65 V with ADC/DAC/VREFINT limitations). Decouple with 100 nF + 1 uF to VSSA.
10	PA0-WKUP1	bidirectional	GPIO PA0 or standby-mode wake-up input WKUP1. Alt functions USART2_CTS/TIM2_CH1_ETR; additional analog ADC_IN0/COMP1_INP/RTC_TAMP2. 5 V-tolerant FT I/O.
11	PA1	bidirectional	GPIO PA1. Alt functions USART2_RTS/TIM2_CH2/LCD_SEG0; additional analog ADC_IN1/COMP1_INP. 5 V-tolerant FT I/O.
12	PA2	bidirectional	GPIO PA2. Alt functions USART2_TX/TIM2_CH3/TIM9_CH1/LCD_SEG1; additional analog ADC_IN2/COMP1_INP. 5 V-tolerant FT I/O.
13	PA3	bidirectional	GPIO PA3. Alt functions USART2_RX/TIM2_CH4/TIM9_CH2/LCD_SEG2; additional analog ADC_IN3/COMP1_INP. Standard 3.3 V TC I/O.
14	PA4	bidirectional	GPIO PA4. Alt functions SPI1_NSS/USART2_CK; additional analog ADC_IN4/DAC_OUT1/COMP1_INP. Standard 3.3 V TC I/O.
15	PA5	bidirectional	GPIO PA5. Alt functions SPI1_SCK/TIM2_CH1_ETR; additional analog ADC_IN5/DAC_OUT2/COMP1_INP. Standard 3.3 V TC I/O.
16	PA6	bidirectional	GPIO PA6. Alt functions SPI1_MISO/TIM3_CH1/LCD_SEG3/TIM10_CH1; additional analog ADC_IN6/COMP1_INP. 5 V-tolerant FT I/O.
17	PA7	bidirectional	GPIO PA7. Alt functions SPI1_MOSI/TIM3_CH2/LCD_SEG4/TIM11_CH1; additional analog ADC_IN7/COMP1_INP. 5 V-tolerant FT I/O.
18	PB0	bidirectional	GPIO PB0. Alt functions TIM3_CH3/LCD_SEG5; additional analog ADC_IN8/COMP1_INP/VREF_OUT/VLCDRAIL3. Standard 3.3 V TC I/O.
19	PB1	bidirectional	GPIO PB1. Alt functions TIM3_CH4/LCD_SEG6; additional analog ADC_IN9/COMP1_INP/VREF_OUT. 5 V-tolerant FT I/O.
20	PB2/BOOT1	bidirectional	GPIO PB2, also latched at reset as BOOT1 boot-mode select bit; additional VLCDRAIL1. 5 V-tolerant FT I/O.
21	PB10	bidirectional	GPIO PB10. Alt functions I2C2_SCL/USART3_TX/TIM2_CH3/LCD_SEG10. 5 V-tolerant FT I/O.
22	PB11	bidirectional	GPIO PB11. Alt functions I2C2_SDA/USART3_RX/TIM2_CH4/LCD_SEG11. 5 V-tolerant FT I/O.
23	VSS_1	power_in	Digital ground return for the digital core and I/O ring (VDD_1 pair).
24	VDD_1	power_in	Digital supply, 1.65-3.6 V. All VDD pins must be tied together and decoupled locally with 100 nF to the paired VSS.
25	PB12	bidirectional	GPIO PB12. Alt functions SPI2_NSS/I2C2_SMBA/USART3_CK/LCD_SEG12/TIM10_CH1; additional analog ADC_IN18/COMP1_INP/VLCDRAIL2. 5 V-tolerant FT I/O.
26	PB13	bidirectional	GPIO PB13. Alt functions SPI2_SCK/USART3_CTS/LCD_SEG13/TIM9_CH1; additional analog ADC_IN19/COMP1_INP. 5 V-tolerant FT I/O.
27	PB14	bidirectional	GPIO PB14. Alt functions SPI2_MISO/USART3_RTS/LCD_SEG14/TIM9_CH2; additional analog ADC_IN20/COMP1_INP. 5 V-tolerant FT I/O.
28	PB15	bidirectional	GPIO PB15. Alt functions SPI2_MOSI/LCD_SEG15/TIM11_CH1; additional analog ADC_IN21/COMP1_INP/RTC_REFIN. 5 V-tolerant FT I/O.
29	PA8	bidirectional	GPIO PA8. Alt functions USART1_CK/MCO (master clock output)/LCD_COM0. 5 V-tolerant FT I/O.
30	PA9	bidirectional	GPIO PA9. Alt functions USART1_TX/LCD_COM1. 5 V-tolerant FT I/O.
31	PA10	bidirectional	GPIO PA10. Alt functions USART1_RX/LCD_COM2. 5 V-tolerant FT I/O.
32	PA11	bidirectional	GPIO PA11. Alt functions USART1_CTS/SPI1_MISO; additional function USB_DM (USB 2.0 FS D-). 5 V-tolerant FT I/O.
33	PA12	bidirectional	GPIO PA12. Alt functions USART1_RTS/SPI1_MOSI; additional function USB_DP (USB 2.0 FS D+). 5 V-tolerant FT I/O.
34	PA13	bidirectional	GPIO PA13, default alt function JTMS-SWDIO (JTAG mode select / Serial Wire Data). 5 V-tolerant FT I/O.
35	VSS_2	power_in	Digital ground return paired with VDD_2.
36	VDD_2	power_in	Digital supply, 1.65-3.6 V, paired with VSS_2. Decouple locally with 100 nF.
37	PA14	bidirectional	GPIO PA14, default alt function JTCK-SWCLK (JTAG clock / Serial Wire clock). 5 V-tolerant FT I/O.
38	PA15	bidirectional	GPIO PA15, default alt function JTDI (JTAG data-in). Alt functions TIM2_CH1_ETR/SPI1_NSS/LCD_SEG17. 5 V-tolerant FT I/O.
39	PB3	bidirectional	GPIO PB3, default alt function JTDO (JTAG data-out); alt TIM2_CH2/SPI1_SCK/LCD_SEG7; additional COMP2_INM. 5 V-tolerant FT I/O.
40	PB4	bidirectional	GPIO PB4, default alt function NJTRST (JTAG reset, active low with internal pull-up); alt TIM3_CH1/SPI1_MISO/LCD_SEG8; additional COMP2_INP. 5 V-tolerant FT I/O.
41	PB5	bidirectional	GPIO PB5. Alt functions I2C1_SMBA/TIM3_CH2/SPI1_MOSI/LCD_SEG9; additional COMP2_INP. 5 V-tolerant FT I/O.
42	PB6	bidirectional	GPIO PB6. Alt functions I2C1_SCL/TIM4_CH1/USART1_TX. 5 V-tolerant FT I/O with true open-drain option for I2C.
43	PB7	bidirectional	GPIO PB7. Alt functions I2C1_SDA/TIM4_CH2/USART1_RX; additional PVD_IN (programmable voltage detector input). 5 V-tolerant FT I/O.
44	BOOT0	input	Dedicated boot-mode select input, latched on the rising edge of NRST. Together with BOOT1 (PB2) selects boot from Flash, System memory or SRAM.
45	PB8	bidirectional	GPIO PB8. Alt functions TIM4_CH3/I2C1_SCL/LCD_SEG16/TIM10_CH1. 5 V-tolerant FT I/O.
46	PB9	bidirectional	GPIO PB9. Alt functions TIM4_CH4/I2C1_SDA/LCD_COM3/TIM11_CH1. 5 V-tolerant FT I/O.
47	VSS_3	power_in	Digital ground return paired with VDD_3.
48	VDD_3	power_in	Digital supply, 1.65-3.6 V, paired with VSS_3. Decouple locally with 100 nF.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-48(7x7)
Category	MCU
Pins	48

Ordering variants

Same part, different packaging or reel option.

STM32L151CBT6A
STM32L151C8T6A
STM32L151C6T6A
STM32L151CBU6A
STM32L151C8U6A
STM32L151C6U6A
STM32L151RBT6A
STM32L151R8T6A
STM32L151R6T6A
STM32L151RBY6A
STM32L151R8Y6A
STM32L151R6Y6A
STM32L151VBT6A
STM32L151V8T6A
STM32L151V6T6A
STM32L151VBH6A
STM32L151V8H6A
STM32L151V6H6A

CAD (KiCad official)

Symbol: STM32L151CBT6A
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`stm32l151cbt6a.step`	617 KB	You want the bare part, or you mark your own boards.
`stm32l151cbt6a-etched.step`	4.6 MB	You want the part with `STM32L151CBT6A` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1169 faces against 747 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (130 pp, sha256 e5e0ab791f4e7879, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF