STM32H7B0VBT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PE2	bidirectional	General-purpose I/O port E bit 2. 5 V tolerant (FT), high-speed low-voltage capable (_h2). Muxed AFs include TRACECLK, SAI1_CK1/MCLK_A, SPI4_SCK, OCTOSPIM_P1_IO2, USART10_RX, FMC_A23.
2	PE3	bidirectional	General-purpose I/O port E bit 3. 5 V tolerant (FT_h2). AFs: TRACED0, TIM15_BKIN, SAI1_SD_B, USART10_TX, FMC_A19.
3	PE4	bidirectional	General-purpose I/O port E bit 4. 5 V tolerant (FT_h2). AFs include TRACED1, SAI1_D2, DFSDM1_DATIN3, SPI4_NSS, FMC_A20, DCMI_D4, LCD_B0.
4	PE5	bidirectional	General-purpose I/O port E bit 5. 5 V tolerant (FT_h2). AFs include TRACED2, SAI1_CK2, DFSDM1_CKIN3, TIM15_CH1, SPI4_MISO, FMC_A21, DCMI_D6, LCD_G0.
5	PE6	bidirectional	General-purpose I/O port E bit 6. 5 V tolerant (FT_h2). AFs include TRACED3, TIM1_BKIN2, SAI1_D1/SD_A, SPI4_MOSI, FMC_A22, DCMI_D7, LCD_G1.
6	VBAT	power_in	Backup battery input (1.62-3.6 V). Powers the RTC, LSE oscillator, backup registers, and backup SRAM when VDD is absent.
7	PC13	bidirectional	General-purpose I/O port C bit 13, also RTC alarm/tamper output on backup domain. Limited drive strength; use as low-frequency I/O only.
8	PC14-OSC32_IN	bidirectional	General-purpose I/O port C bit 14, or LSE 32.768 kHz crystal input (OSC32_IN) when RTC/LSE oscillator is enabled.
9	PC15-OSC32_OUT	bidirectional	General-purpose I/O port C bit 15, or LSE 32.768 kHz crystal output (OSC32_OUT) when RTC/LSE oscillator is enabled.
10	VSS	power_in	Digital ground reference. Tie to system 0 V plane.
11	VDD	power_in	Digital I/O and internal core supply (1.62-3.6 V). Decouple locally with 100 nF plus bulk cap.
12	PH0-OSC_IN	bidirectional	General-purpose I/O port H bit 0, or HSE crystal input (OSC_IN, 4-50 MHz) when HSE oscillator is enabled.
13	PH1-OSC_OUT	bidirectional	General-purpose I/O port H bit 1, or HSE crystal output (OSC_OUT) when HSE oscillator is enabled.
14	NRST	bidirectional	Bidirectional device reset, active-low, with internal weak pull-up (~40 kΩ). Assertion resets the MCU; open-drain output on internal reset.
15	PC0	bidirectional	General-purpose I/O port C bit 0 with analog capability (ADC1/ADC2 IN10). 3.3 V tolerant analog-tolerant I/O.
16	PC1	bidirectional	General-purpose I/O port C bit 1 with analog capability (ADC1/ADC2 IN11, ETH_MDC AF).
17	PC2_C	bidirectional	Dual-pad ADC input PC2_C (direct ADC connection variant of PC2). Analog-only routing to ADC2 differential/single-ended input.
18	PC3_C	bidirectional	Dual-pad ADC input PC3_C (direct ADC connection variant of PC3). Analog-only routing to ADC2 differential/single-ended input.
19	VSSA	power_in	Analog ground reference for ADC/DAC/VREF and analog peripherals. Tie to VSS at a single point near the ADC.
20	VREF+	power_in	Positive ADC/DAC reference voltage input (1.62 V to VDDA). Determines full-scale for ADC and DAC.
21	VDDA	power_in	Analog supply for ADCs, DACs, comparators, op-amps, and internal reference (1.62-3.6 V). Decouple with 100 nF + 1 µF close to pin.
22	PA0	bidirectional	General-purpose I/O port A bit 0 with analog capability (ADC1 IN16). Common WKUP1 additional function and TIM2_CH1/TIM5_CH1 AFs.
23	PA1	bidirectional	General-purpose I/O port A bit 1 with analog capability (ADC1 IN17). Popular ETH_REF_CLK and TIM2_CH2 AFs.
24	PA2	bidirectional	General-purpose I/O port A bit 2 with analog capability (ADC1/ADC2 IN14). Common USART2_TX and ETH_MDIO AFs.
25	PA3	bidirectional	General-purpose I/O port A bit 3 with analog capability (ADC1/ADC2 IN15). Common USART2_RX and LCD_B5 AFs.
26	VSS	power_in	Digital ground reference.
27	VDD	power_in	Digital I/O and internal core supply (1.62-3.6 V).
28	PA4	bidirectional	General-purpose I/O port A bit 4 with analog capability (ADC2 IN18, DAC1_OUT1). Common SPI1_NSS/SPI3_NSS and I2S3_WS AFs.
29	PA5	bidirectional	General-purpose I/O port A bit 5 with analog capability (ADC2 IN19, DAC1_OUT2). Common SPI1_SCK and TIM2_CH1_ETR AFs.
30	PA6	bidirectional	General-purpose I/O port A bit 6 with analog capability (ADC1/ADC2 IN3). Common SPI1_MISO, TIM3_CH1, and DCMI_PIXCLK AFs.
31	PA7	bidirectional	General-purpose I/O port A bit 7 with analog capability (ADC1/ADC2 IN7). Common SPI1_MOSI, TIM3_CH2, ETH_MII_RX_DV AFs.
32	PC4	bidirectional	General-purpose I/O port C bit 4 with analog capability (ADC1/ADC2 IN4). Common ETH_MII_RX_D0/RMII_RXD0 AF.
33	PC5	bidirectional	General-purpose I/O port C bit 5 with analog capability (ADC1/ADC2 IN8). Common ETH_MII_RX_D1/RMII_RXD1 AF.
34	PB0	bidirectional	General-purpose I/O port B bit 0 with analog capability (ADC1/ADC2 IN9). Common TIM1_CH2N, TIM3_CH3 AFs.
35	PB1	bidirectional	General-purpose I/O port B bit 1 with analog capability (ADC1/ADC2 IN5). Common TIM1_CH3N, TIM3_CH4 AFs.
36	PB2	bidirectional	General-purpose I/O port B bit 2. 5 V tolerant. Common SAI1_D1/SD_A, RTC_OUT AFs; also BOOT1 legacy on some parts.
37	PE7	bidirectional	General-purpose I/O port E bit 7. 5 V tolerant (FT_h2). Common TIM1_ETR, UART7_RX, FMC_D4 AFs.
38	PE8	bidirectional	General-purpose I/O port E bit 8. 5 V tolerant (FT_h2). Common TIM1_CH1N, UART7_TX, FMC_D5 AFs.
39	PE9	bidirectional	General-purpose I/O port E bit 9. 5 V tolerant (FT_h2). Common TIM1_CH1, FMC_D6 AFs.
40	PE10	bidirectional	General-purpose I/O port E bit 10. 5 V tolerant (FT_h2). Common TIM1_CH2N, FMC_D7 AFs.
41	PE11	bidirectional	General-purpose I/O port E bit 11. 5 V tolerant (FT_h2). Common TIM1_CH2, SPI4_NSS, FMC_D8 AFs.
42	PE12	bidirectional	General-purpose I/O port E bit 12. 5 V tolerant (FT_h2). Common TIM1_CH3N, SPI4_SCK, FMC_D9 AFs.
43	PE13	bidirectional	General-purpose I/O port E bit 13. 5 V tolerant (FT_h2). Common TIM1_CH3, SPI4_MISO, FMC_D10 AFs.
44	PE14	bidirectional	General-purpose I/O port E bit 14. 5 V tolerant (FT_h2). Common TIM1_CH4, SPI4_MOSI, FMC_D11 AFs.
45	PE15	bidirectional	General-purpose I/O port E bit 15. 5 V tolerant (FT_h2). Common TIM1_BKIN, FMC_D12 AFs.
46	PB10	bidirectional	General-purpose I/O port B bit 10. 5 V tolerant. Common I2C2_SCL, SPI2_SCK, USART3_TX, ETH_MII_RX_ER AFs.
47	PB11	bidirectional	General-purpose I/O port B bit 11. 5 V tolerant. Common I2C2_SDA, USART3_RX, ETH_MII_TX_EN/RMII_TX_EN AFs.
48	VCAP	passive	Internal LDO decoupling cap for core 1.2 V regulator. Connect a 2.2 µF low-ESR ceramic to VSS. Do not drive externally.
49	VSS	power_in	Digital ground reference.
50	VDD	power_in	Digital I/O and internal core supply (1.62-3.6 V).
51	PB12	bidirectional	General-purpose I/O port B bit 12. 5 V tolerant. Common CAN2_RX, SPI2_NSS, USART3_CK, USB_OTG_HS_ULPI_D5 AFs.
52	PB13	bidirectional	General-purpose I/O port B bit 13. 5 V tolerant. Common CAN2_TX, SPI2_SCK, USART3_CTS, USB_OTG_HS_ULPI_D6 AFs.
53	PB14	bidirectional	General-purpose I/O port B bit 14. 5 V tolerant. Common USART1_TX, SPI2_MISO, TIM12_CH1, USB_OTG_HS_DM AFs.
54	PB15	bidirectional	General-purpose I/O port B bit 15. 5 V tolerant. Common USART1_RX, SPI2_MOSI, TIM12_CH2, USB_OTG_HS_DP AFs.
55	PD8	bidirectional	General-purpose I/O port D bit 8. 5 V tolerant. Common USART3_TX, FMC_D13, LCD_B3 AFs.
56	PD9	bidirectional	General-purpose I/O port D bit 9. 5 V tolerant. Common USART3_RX, FMC_D14 AFs.
57	PD10	bidirectional	General-purpose I/O port D bit 10. 5 V tolerant. Common USART3_CK, FMC_D15, LCD_B3 AFs.
58	PD11	bidirectional	General-purpose I/O port D bit 11. 5 V tolerant. Common USART3_CTS, FMC_A16, OCTOSPIM_P1_IO0 AFs.
59	PD12	bidirectional	General-purpose I/O port D bit 12. 5 V tolerant. Common USART3_RTS, TIM4_CH1, FMC_A17, OCTOSPIM_P1_IO1 AFs.
60	PD13	bidirectional	General-purpose I/O port D bit 13. 5 V tolerant. Common TIM4_CH2, FMC_A18, OCTOSPIM_P1_IO3 AFs.
61	PD14	bidirectional	General-purpose I/O port D bit 14. 5 V tolerant. Common TIM4_CH3, FMC_D0 AFs.
62	PD15	bidirectional	General-purpose I/O port D bit 15. 5 V tolerant. Common TIM4_CH4, FMC_D1 AFs.
63	PC6	bidirectional	General-purpose I/O port C bit 6. 5 V tolerant. Common TIM3_CH1, TIM8_CH1, SDMMC1_D6, USART6_TX, DCMI_D0, LCD_HSYNC AFs.
64	PC7	bidirectional	General-purpose I/O port C bit 7. 5 V tolerant. Common TIM3_CH2, TIM8_CH2, SDMMC1_D7, USART6_RX, DCMI_D1 AFs.
65	PC8	bidirectional	General-purpose I/O port C bit 8. 5 V tolerant. Common TIM3_CH3, TIM8_CH3, SDMMC1_D0, USART6_CK, DCMI_D2 AFs.
66	PC9	bidirectional	General-purpose I/O port C bit 9. 5 V tolerant. Common TIM3_CH4, TIM8_CH4, SDMMC1_D1, I2C3_SDA, DCMI_D3 AFs.
67	PA8	bidirectional	General-purpose I/O port A bit 8. 5 V tolerant. Common TIM1_CH1, USART1_CK, I2C3_SCL, MCO1, USB_OTG_FS_SOF AFs.
68	PA9	bidirectional	General-purpose I/O port A bit 9. 5 V tolerant. Common TIM1_CH2, USART1_TX, I2C3_SMBA, DCMI_D0 AFs.
69	PA10	bidirectional	General-purpose I/O port A bit 10. 5 V tolerant. Common TIM1_CH3, USART1_RX, USB_OTG_FS_ID, DCMI_D1 AFs.
70	PA11	bidirectional	General-purpose I/O port A bit 11 / USB_OTG_FS_DM data line minus. 5 V tolerant. Also TIM1_CH4, USART1_CTS, CAN1_RX AFs.
71	PA12	bidirectional	General-purpose I/O port A bit 12 / USB_OTG_FS_DP data line plus. 5 V tolerant. Also TIM1_ETR, USART1_RTS, CAN1_TX AFs.
72	PA13	bidirectional	General-purpose I/O port A bit 13 / SWDIO (Serial Wire Debug data I/O) / JTMS. 5 V tolerant. Default AF0 on reset for debug.
73	VCAP	passive	Internal LDO decoupling cap for core 1.2 V regulator. Connect a 2.2 µF low-ESR ceramic to VSS.
74	VSS	power_in	Digital ground reference.
75	VDD	power_in	Digital I/O and internal core supply (1.62-3.6 V).
76	PA14	bidirectional	General-purpose I/O port A bit 14 / SWCLK (Serial Wire Debug clock) / JTCK. 5 V tolerant. Default AF0 on reset for debug.
77	PA15	bidirectional	General-purpose I/O port A bit 15 / JTDI. 5 V tolerant. Common TIM2_CH1_ETR, SPI3_NSS/I2S3_WS AFs.
78	PC10	bidirectional	General-purpose I/O port C bit 10. 5 V tolerant. Common SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, SDMMC1_D2 AFs.
79	PC11	bidirectional	General-purpose I/O port C bit 11. 5 V tolerant. Common SPI3_MISO, USART3_RX, UART4_RX, SDMMC1_D3 AFs.
80	PC12	bidirectional	General-purpose I/O port C bit 12. 5 V tolerant. Common SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDMMC1_CK AFs.
81	PD0	bidirectional	General-purpose I/O port D bit 0. 5 V tolerant. Common CAN1_RX, UART4_RX, FMC_D2 AFs.
82	PD1	bidirectional	General-purpose I/O port D bit 1. 5 V tolerant. Common CAN1_TX, FMC_D3 AFs.
83	PD2	bidirectional	General-purpose I/O port D bit 2. 5 V tolerant. Common TIM3_ETR, UART5_RX, SDMMC1_CMD, DCMI_D11 AFs.
84	PD3	bidirectional	General-purpose I/O port D bit 3. 5 V tolerant. Common USART2_CTS, SPI2_SCK, FMC_CLK, DCMI_D5 AFs.
85	PD4	bidirectional	General-purpose I/O port D bit 4. 5 V tolerant. Common USART2_RTS, FMC_NOE, SAI1_D1 AFs.
86	PD5	bidirectional	General-purpose I/O port D bit 5. 5 V tolerant. Common USART2_TX, FMC_NWE AFs.
87	PD6	bidirectional	General-purpose I/O port D bit 6. 5 V tolerant. Common USART2_RX, SPI3_MOSI/I2S3_SD, SDMMC2_CK, FMC_NWAIT, DCMI_D10 AFs.
88	PD7	bidirectional	General-purpose I/O port D bit 7. 5 V tolerant. Common USART2_CK, SDMMC2_CMD, FMC_NE1 AFs.
89	PB3	bidirectional	General-purpose I/O port B bit 3 / SWO / JTDO. 5 V tolerant. Common SPI1_SCK/SPI3_SCK, TIM2_CH2 AFs.
90	PB4	bidirectional	General-purpose I/O port B bit 4 / NJTRST. 5 V tolerant. Common SPI1_MISO/SPI3_MISO, TIM3_CH1 AFs.
91	PB5	bidirectional	General-purpose I/O port B bit 5. 5 V tolerant. Common I2C1_SMBA, SPI1_MOSI/SPI3_MOSI, CAN2_RX, ETH_MII_TX_D3 AFs.
92	PB6	bidirectional	General-purpose I/O port B bit 6. 5 V tolerant (FT_f, I2C FM+ capable). Common I2C1_SCL, USART1_TX, CAN2_TX, DCMI_D5 AFs.
93	PB7	bidirectional	General-purpose I/O port B bit 7. 5 V tolerant (FT_f). Common I2C1_SDA, USART1_RX, FMC_NL, DCMI_VSYNC AFs.
94	BOOT0	input	Boot mode select pin, sampled at reset. 0 = boot from user Flash / 1 = boot from system memory or RAM per option bytes. Dedicated BOOT pin (no GPIO function).
95	PB8	bidirectional	General-purpose I/O port B bit 8. 5 V tolerant (FT_f). Common I2C1_SCL, TIM4_CH3, CAN1_RX, ETH_MII_TXD3, SDMMC1_D4 AFs.
96	PB9	bidirectional	General-purpose I/O port B bit 9. 5 V tolerant (FT_f). Common I2C1_SDA, TIM4_CH4, CAN1_TX, SDMMC1_D5, I2C4_SDA AFs.
97	PE0	bidirectional	General-purpose I/O port E bit 0. 5 V tolerant (FT_h2). Common TIM4_ETR, UART8_RX, FMC_NBL0, DCMI_D2 AFs.
98	PE1	bidirectional	General-purpose I/O port E bit 1. 5 V tolerant (FT_h2). Common UART8_TX, FMC_NBL1, DCMI_D3 AFs.
99	VSS	power_in	Digital ground reference.
100	VDD	power_in	Digital I/O and internal core supply (1.62-3.6 V).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-100(14x14)
Category	MCU
Pins	100

Ordering variants

Same part, different packaging or reel option.

STM32H7B0VBT6
STM32H7B0VBT6RBT6
STM32H7B0VBT6ZBT6
STM32H7B0VBT6IBT6
STM32H7B0VBT6AB
STM32H7B0VBT6IB

CAD (KiCad official)

Symbol: STM32H7B0VBT6
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`stm32h7b0vbt6.step`	1305 KB	You want the bare part, or you mark your own boards.
`stm32h7b0vbt6-etched.step`	7.4 MB	You want the part with `STM32H7B0VBT6` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1847 faces against 1535 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (202 pp, sha256 eeb37a566bb0f97e, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF