component

STM32F103VFT6

Public Unreviewed

by Ray

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentmcustm32f103vft6
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Symbol & Footprint

Schematic Symbol

Open full view ↗

PCB Footprint

Open full view ↗
Contents

README

markdown

STM32F103VFT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32F103VFT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional Port E bit 2. 5V-tolerant GPIO. Alt: TRACECK / FSMC_A23.
2 PE3 bidirectional Port E bit 3. 5V-tolerant GPIO. Alt: TRACED0 / FSMC_A19.
3 PE4 bidirectional Port E bit 4. 5V-tolerant GPIO. Alt: TRACED1 / FSMC_A20.
4 PE5 bidirectional Port E bit 5. 5V-tolerant GPIO. Alt: TRACED2 / FSMC_A21 / TIM9_CH1.
5 PE6 bidirectional Port E bit 6. 5V-tolerant GPIO. Alt: TRACED3 / FSMC_A22 / TIM9_CH2.
6 VBAT power_in Backup-domain supply (1.8-3.6 V). Powers RTC, LSE oscillator and backup registers when VDD is absent; tie to VDD if backup domain is unused.
7 PC13-TAMPER-RTC bidirectional PC13 in backup domain. Alt: TAMPER-RTC. Supplied via the backup power switch, so output drive is limited to 2 MHz / 3 mA / 30 pF; do not use as a current source.
8 PC14-OSC32_IN bidirectional PC14 in backup domain / 32.768 kHz LSE crystal input. Limited-drive backup-domain GPIO when not used as OSC32_IN.
9 PC15-OSC32_OUT bidirectional PC15 in backup domain / 32.768 kHz LSE crystal output. Limited-drive backup-domain GPIO when not used as OSC32_OUT.
10 VSS_5 power_in Digital ground. Connect to system ground plane.
11 VDD_5 power_in Digital core/IO supply (2.0-3.6 V). Decouple with 100 nF close to pin.
12 OSC_IN input Main HSE oscillator input (4-16 MHz crystal or external clock). Can be remapped to PD0 by software.
13 OSC_OUT output Main HSE oscillator output for crystal. Can be remapped to PD1 by software.
14 NRST bidirectional Active-low bidirectional reset input/open-drain output with internal pull-up. Drive low to reset the device; the MCU also asserts it when an internal reset source triggers.
15 PC0 bidirectional Port C bit 0. Alt: ADC123_IN10.
16 PC1 bidirectional Port C bit 1. Alt: ADC123_IN11.
17 PC2 bidirectional Port C bit 2. Alt: ADC123_IN12.
18 PC3 bidirectional Port C bit 3. Alt: ADC123_IN13.
19 VSSA power_in Analog ground reference for ADC/DAC and analog blocks. Connect to VSS with a single-point analog star.
20 VREF- power_in Negative ADC/DAC reference input. Typically tied to VSSA.
21 VREF+ power_in Positive ADC/DAC reference input (2.4 V to VDDA). Decouple with 100 nF + 1 uF close to pin.
22 VDDA power_in Analog supply for ADC/DAC/reset/PLL (2.0-3.6 V). Filter/decouple from digital VDD.
23 PA0-WKUP bidirectional Port A bit 0. Alt: WKUP / USART2_CTS / ADC123_IN0 / TIM2_CH1_ETR / TIM5_CH1 / TIM8_ETR. Also serves as Standby-mode wake-up input.
24 PA1 bidirectional Port A bit 1. Alt: USART2_RTS / ADC123_IN1 / TIM5_CH2 / TIM2_CH2.
25 PA2 bidirectional Port A bit 2. Alt: USART2_TX / TIM5_CH3 / ADC123_IN2 / TIM9_CH1 / TIM2_CH3.
26 PA3 bidirectional Port A bit 3. Alt: USART2_RX / TIM5_CH4 / ADC123_IN3 / TIM2_CH4 / TIM9_CH2.
27 VSS_4 power_in Digital ground.
28 VDD_4 power_in Digital core/IO supply (2.0-3.6 V). Decouple with 100 nF close to pin.
29 PA4 bidirectional Port A bit 4. Alt: SPI1_NSS / USART2_CK / DAC_OUT1 / ADC12_IN4.
30 PA5 bidirectional Port A bit 5. Alt: SPI1_SCK / DAC_OUT2 / ADC12_IN5.
31 PA6 bidirectional Port A bit 6. Alt: SPI1_MISO / TIM8_BKIN / ADC12_IN6 / TIM3_CH1 / TIM13_CH1; remap TIM1_BKIN.
32 PA7 bidirectional Port A bit 7. Alt: SPI1_MOSI / TIM8_CH1N / ADC12_IN7 / TIM3_CH2 / TIM14_CH1; remap TIM1_CH1N.
33 PC4 bidirectional Port C bit 4. Alt: ADC12_IN14.
34 PC5 bidirectional Port C bit 5. Alt: ADC12_IN15.
35 PB0 bidirectional Port B bit 0. Alt: ADC12_IN8 / TIM3_CH3 / TIM8_CH2N; remap TIM1_CH2N.
36 PB1 bidirectional Port B bit 1. Alt: ADC12_IN9 / TIM3_CH4 / TIM8_CH3N; remap TIM1_CH3N.
37 PB2/BOOT1 bidirectional Port B bit 2. 5V-tolerant GPIO after reset; sampled as BOOT1 at reset to select boot mode along with BOOT0.
38 PE7 bidirectional Port E bit 7. 5V-tolerant. Alt: FSMC_D4; remap TIM1_ETR.
39 PE8 bidirectional Port E bit 8. 5V-tolerant. Alt: FSMC_D5; remap TIM1_CH1N.
40 PE9 bidirectional Port E bit 9. 5V-tolerant. Alt: FSMC_D6; remap TIM1_CH1.
41 PE10 bidirectional Port E bit 10. 5V-tolerant. Alt: FSMC_D7; remap TIM1_CH2N.
42 PE11 bidirectional Port E bit 11. 5V-tolerant. Alt: FSMC_D8; remap TIM1_CH2.
43 PE12 bidirectional Port E bit 12. 5V-tolerant. Alt: FSMC_D9; remap TIM1_CH3N.
44 PE13 bidirectional Port E bit 13. 5V-tolerant. Alt: FSMC_D10; remap TIM1_CH3.
45 PE14 bidirectional Port E bit 14. 5V-tolerant. Alt: FSMC_D11; remap TIM1_CH4.
46 PE15 bidirectional Port E bit 15. 5V-tolerant. Alt: FSMC_D12; remap TIM1_BKIN.
47 PB10 bidirectional Port B bit 10. 5V-tolerant. Alt: I2C2_SCL / USART3_TX; remap TIM2_CH3.
48 PB11 bidirectional Port B bit 11. 5V-tolerant. Alt: I2C2_SDA / USART3_RX; remap TIM2_CH4.
49 VSS_1 power_in Digital ground.
50 VDD_1 power_in Digital core/IO supply (2.0-3.6 V). Decouple with 100 nF close to pin.
51 PB12 bidirectional Port B bit 12. 5V-tolerant. Alt: SPI2_NSS / I2S2_WS / I2C2_SMBA / USART3_CK / TIM1_BKIN.
52 PB13 bidirectional Port B bit 13. 5V-tolerant. Alt: SPI2_SCK / I2S2_CK / USART3_CTS / TIM1_CH1N.
53 PB14 bidirectional Port B bit 14. 5V-tolerant. Alt: SPI2_MISO / TIM1_CH2N / USART3_RTS / TIM12_CH1.
54 PB15 bidirectional Port B bit 15. 5V-tolerant. Alt: SPI2_MOSI / I2S2_SD / TIM1_CH3N / TIM12_CH2.
55 PD8 bidirectional Port D bit 8. 5V-tolerant. Alt: FSMC_D13; remap USART3_TX.
56 PD9 bidirectional Port D bit 9. 5V-tolerant. Alt: FSMC_D14; remap USART3_RX.
57 PD10 bidirectional Port D bit 10. 5V-tolerant. Alt: FSMC_D15; remap USART3_CK.
58 PD11 bidirectional Port D bit 11. 5V-tolerant. Alt: FSMC_A16; remap USART3_CTS.
59 PD12 bidirectional Port D bit 12. 5V-tolerant. Alt: FSMC_A17 / TIM4_CH1; remap USART3_RTS.
60 PD13 bidirectional Port D bit 13. 5V-tolerant. Alt: FSMC_A18 / TIM4_CH2.
61 PD14 bidirectional Port D bit 14. 5V-tolerant. Alt: FSMC_D0 / TIM4_CH3.
62 PD15 bidirectional Port D bit 15. 5V-tolerant. Alt: FSMC_D1 / TIM4_CH4.
63 PC6 bidirectional Port C bit 6. 5V-tolerant. Alt: I2S2_MCK / TIM8_CH1 / SDIO_D6; remap TIM3_CH1.
64 PC7 bidirectional Port C bit 7. 5V-tolerant. Alt: I2S3_MCK / TIM8_CH2 / SDIO_D7; remap TIM3_CH2.
65 PC8 bidirectional Port C bit 8. 5V-tolerant. Alt: TIM8_CH3 / SDIO_D0; remap TIM3_CH3.
66 PC9 bidirectional Port C bit 9. 5V-tolerant. Alt: TIM8_CH4 / SDIO_D1; remap TIM3_CH4.
67 PA8 bidirectional Port A bit 8. 5V-tolerant. Alt: USART1_CK / TIM1_CH1 / MCO.
68 PA9 bidirectional Port A bit 9. 5V-tolerant. Alt: USART1_TX / TIM1_CH2.
69 PA10 bidirectional Port A bit 10. 5V-tolerant. Alt: USART1_RX / TIM1_CH3.
70 PA11 bidirectional Port A bit 11. 5V-tolerant. Alt: USART1_CTS / USBDM / CAN_RX / TIM1_CH4.
71 PA12 bidirectional Port A bit 12. 5V-tolerant. Alt: USART1_RTS / USBDP / CAN_TX / TIM1_ETR.
72 PA13 bidirectional Port A bit 13. 5V-tolerant. After reset: JTMS-SWDIO (SWD data / JTAG TMS). Remap: PA13 GPIO.
73 NC unconnected Not connected. Leave floating on the PCB.
74 VSS_2 power_in Digital ground.
75 VDD_2 power_in Digital core/IO supply (2.0-3.6 V). Decouple with 100 nF close to pin.
76 PA14 bidirectional Port A bit 14. 5V-tolerant. After reset: JTCK-SWCLK (SWD clock / JTAG TCK). Remap: PA14 GPIO.
77 PA15 bidirectional Port A bit 15. 5V-tolerant. After reset: JTDI. Alt: SPI3_NSS / I2S3_WS; remap TIM2_CH1_ETR / PA15 / SPI1_NSS.
78 PC10 bidirectional Port C bit 10. 5V-tolerant. Alt: UART4_TX / SDIO_D2; remap USART3_TX.
79 PC11 bidirectional Port C bit 11. 5V-tolerant. Alt: UART4_RX / SDIO_D3; remap USART3_RX.
80 PC12 bidirectional Port C bit 12. 5V-tolerant. Alt: UART5_TX / SDIO_CK; remap USART3_CK.
81 PD0 bidirectional Port D bit 0. 5V-tolerant. Alt: FSMC_D2; remap CAN_RX. Available directly on LQFP100 (no OSC_IN remap needed).
82 PD1 bidirectional Port D bit 1. 5V-tolerant. Alt: FSMC_D3; remap CAN_TX. Available directly on LQFP100 (no OSC_OUT remap needed).
83 PD2 bidirectional Port D bit 2. 5V-tolerant. Alt: TIM3_ETR / UART5_RX / SDIO_CMD.
84 PD3 bidirectional Port D bit 3. 5V-tolerant. Alt: FSMC_CLK; remap USART2_CTS.
85 PD4 bidirectional Port D bit 4. 5V-tolerant. Alt: FSMC_NOE; remap USART2_RTS.
86 PD5 bidirectional Port D bit 5. 5V-tolerant. Alt: FSMC_NWE; remap USART2_TX.
87 PD6 bidirectional Port D bit 6. 5V-tolerant. Alt: FSMC_NWAIT; remap USART2_RX.
88 PD7 bidirectional Port D bit 7. 5V-tolerant. Alt: FSMC_NE1 / FSMC_NCE2; remap USART2_CK.
89 PB3 bidirectional Port B bit 3. 5V-tolerant. After reset: JTDO. Alt: SPI3_SCK / I2S3_CK; remap PB3/TRACESWO/TIM2_CH2/SPI1_SCK.
90 PB4 bidirectional Port B bit 4. 5V-tolerant. After reset: NJTRST. Alt: SPI3_MISO; remap PB4/TIM3_CH1/SPI1_MISO.
91 PB5 bidirectional Port B bit 5. Not 5V-tolerant. Alt: I2C1_SMBA / SPI3_MOSI / I2S3_SD; remap TIM3_CH2 / SPI1_MOSI.
92 PB6 bidirectional Port B bit 6. 5V-tolerant. Alt: I2C1_SCL / TIM4_CH1; remap USART1_TX.
93 PB7 bidirectional Port B bit 7. 5V-tolerant. Alt: I2C1_SDA / FSMC_NADV / TIM4_CH2; remap USART1_RX.
94 BOOT0 input Boot mode select input, sampled at reset together with BOOT1 to choose the boot memory (main Flash / system memory / embedded SRAM). Must be tied via resistor.
95 PB8 bidirectional Port B bit 8. 5V-tolerant. Alt: TIM4_CH3 / SDIO_D4 / TIM10_CH1; remap I2C1_SCL / CAN_RX.
96 PB9 bidirectional Port B bit 9. 5V-tolerant. Alt: TIM4_CH4 / SDIO_D5 / TIM11_CH1; remap I2C1_SDA / CAN_TX.
97 PE0 bidirectional Port E bit 0. 5V-tolerant. Alt: TIM4_ETR / FSMC_NBL0.
98 PE1 bidirectional Port E bit 1. 5V-tolerant. Alt: FSMC_NBL1.
99 VSS_3 power_in Digital ground.
100 VDD_3 power_in Digital core/IO supply (2.0-3.6 V). Decouple with 100 nF close to pin.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category MCU
Pins 100

Ordering variants

Same part, different packaging or reel option.

  • STM32F103VFT6
  • STM32F103VFT6VFT7
  • STM32F103VFT6VGT6
  • STM32F103VFT6VGT7
  • STM32F103VFT6RFT6
  • STM32F103VFT6RFT7
  • STM32F103VFT6RGT6
  • STM32F103VFT6RGT7
  • STM32F103VFT6ZFT6
  • STM32F103VFT6ZFT7
  • STM32F103VFT6ZGT6
  • STM32F103VFT6ZGT7
  • STM32F103VFT6ZFH6
  • STM32F103VFT6ZFH7
  • STM32F103VFT6ZGH6
  • STM32F103VFT6ZGH7

CAD (KiCad official)

  • Symbol: STM32F103VFT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
stm32f103vft6.step 1305 KB You want the bare part, or you mark your own boards.
stm32f103vft6-etched.step 7.3 MB You want the part with STM32F103VFT6 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1825 faces against 1535 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (120 pp, sha256 d4650f1e5a23ce6e, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF