STM32F103VCT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PE2	bidirectional	GPIO PE2, 5 V tolerant. Alt: TRACECK (ETM trace clock) / FSMC_A23.
2	PE3	bidirectional	GPIO PE3, 5 V tolerant. Alt: TRACED0 / FSMC_A19.
3	PE4	bidirectional	GPIO PE4, 5 V tolerant. Alt: TRACED1 / FSMC_A20.
4	PE5	bidirectional	GPIO PE5, 5 V tolerant. Alt: TRACED2 / FSMC_A21.
5	PE6	bidirectional	GPIO PE6, 5 V tolerant. Alt: TRACED3 / FSMC_A22.
6	VBAT	power_in	Backup battery supply (1.8-3.6 V) for RTC and backup registers when VDD is off.
7	PC13-TAMPER-RTC	bidirectional	PC13 GPIO / TAMPER-RTC. Supplied through the backup domain power switch; limited to 3 mA sink, ≤2 MHz output, 30 pF load; not suitable as a current source.
8	PC14-OSC32_IN	bidirectional	PC14 GPIO / 32.768 kHz LSE oscillator input. Backup-domain pin with limited drive; primary use is LSE crystal.
9	PC15-OSC32_OUT	bidirectional	PC15 GPIO / 32.768 kHz LSE oscillator output. Backup-domain pin with limited drive; primary use is LSE crystal.
10	VSS_5	power_in	Digital ground (0 V).
11	VDD_5	power_in	Digital supply, 2.0-3.6 V. Requires 100 nF decoupling to VSS_5.
12	OSC_IN	input	HSE 4-16 MHz crystal oscillator input (or external clock in bypass mode).
13	OSC_OUT	output	HSE crystal oscillator output.
14	NRST	bidirectional	Active-low bidirectional reset pin with internal pull-up (~40 kΩ). Drive low to reset the MCU.
15	PC0	bidirectional	GPIO PC0. Alt: ADC123_IN10.
16	PC1	bidirectional	GPIO PC1. Alt: ADC123_IN11.
17	PC2	bidirectional	GPIO PC2. Alt: ADC123_IN12.
18	PC3	bidirectional	GPIO PC3. Alt: ADC123_IN13.
19	VSSA	power_in	Analog ground reference for ADC/DAC. Tie to VSS via star ground.
20	VREF-	power_in	Negative reference voltage for ADC. Typically tied to VSSA.
21	VREF+	power_in	Positive reference voltage for ADC (2.4 V to VDDA).
22	VDDA	power_in	Analog supply for ADC/DAC/reset/PLL (2.0-3.6 V).
23	PA0-WKUP	bidirectional	PA0 GPIO / WKUP wake-up input. Alt: USART2_CTS, ADC123_IN0, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR.
24	PA1	bidirectional	GPIO PA1. Alt: USART2_RTS, ADC123_IN1, TIM5_CH2, TIM2_CH2.
25	PA2	bidirectional	GPIO PA2. Alt: USART2_TX, TIM5_CH3, ADC123_IN2, TIM2_CH3.
26	PA3	bidirectional	GPIO PA3. Alt: USART2_RX, TIM5_CH4, ADC123_IN3, TIM2_CH4.
27	VSS_4	power_in	Digital ground (0 V).
28	VDD_4	power_in	Digital supply, 2.0-3.6 V.
29	PA4	bidirectional	GPIO PA4. Alt: SPI1_NSS, USART2_CK, DAC_OUT1, ADC12_IN4.
30	PA5	bidirectional	GPIO PA5. Alt: SPI1_SCK, DAC_OUT2, ADC12_IN5.
31	PA6	bidirectional	GPIO PA6. Alt: SPI1_MISO, TIM8_BKIN, ADC12_IN6, TIM3_CH1; Remap: TIM1_BKIN.
32	PA7	bidirectional	GPIO PA7. Alt: SPI1_MOSI, TIM8_CH1N, ADC12_IN7, TIM3_CH2; Remap: TIM1_CH1N.
33	PC4	bidirectional	GPIO PC4. Alt: ADC12_IN14.
34	PC5	bidirectional	GPIO PC5. Alt: ADC12_IN15.
35	PB0	bidirectional	GPIO PB0. Alt: ADC12_IN8, TIM3_CH3, TIM8_CH2N; Remap: TIM1_CH2N.
36	PB1	bidirectional	GPIO PB1. Alt: ADC12_IN9, TIM3_CH4, TIM8_CH3N; Remap: TIM1_CH3N.
37	PB2/BOOT1	bidirectional	GPIO PB2, 5 V tolerant; also sampled as BOOT1 at reset to select boot memory together with BOOT0.
38	PE7	bidirectional	GPIO PE7, 5 V tolerant. Alt: FSMC_D4; Remap: TIM1_ETR.
39	PE8	bidirectional	GPIO PE8, 5 V tolerant. Alt: FSMC_D5; Remap: TIM1_CH1N.
40	PE9	bidirectional	GPIO PE9, 5 V tolerant. Alt: FSMC_D6; Remap: TIM1_CH1.
41	PE10	bidirectional	GPIO PE10, 5 V tolerant. Alt: FSMC_D7; Remap: TIM1_CH2N.
42	PE11	bidirectional	GPIO PE11, 5 V tolerant. Alt: FSMC_D8; Remap: TIM1_CH2.
43	PE12	bidirectional	GPIO PE12, 5 V tolerant. Alt: FSMC_D9; Remap: TIM1_CH3N.
44	PE13	bidirectional	GPIO PE13, 5 V tolerant. Alt: FSMC_D10; Remap: TIM1_CH3.
45	PE14	bidirectional	GPIO PE14, 5 V tolerant. Alt: FSMC_D11; Remap: TIM1_CH4.
46	PE15	bidirectional	GPIO PE15, 5 V tolerant. Alt: FSMC_D12; Remap: TIM1_BKIN.
47	PB10	bidirectional	GPIO PB10, 5 V tolerant. Alt: I2C2_SCL, USART3_TX; Remap: TIM2_CH3.
48	PB11	bidirectional	GPIO PB11, 5 V tolerant. Alt: I2C2_SDA, USART3_RX; Remap: TIM2_CH4.
49	VSS_1	power_in	Digital ground (0 V).
50	VDD_1	power_in	Digital supply, 2.0-3.6 V.
51	PB12	bidirectional	GPIO PB12, 5 V tolerant. Alt: SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN.
52	PB13	bidirectional	GPIO PB13, 5 V tolerant. Alt: SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N.
53	PB14	bidirectional	GPIO PB14, 5 V tolerant. Alt: SPI2_MISO, TIM1_CH2N, USART3_RTS.
54	PB15	bidirectional	GPIO PB15, 5 V tolerant. Alt: SPI2_MOSI, I2S2_SD, TIM1_CH3N.
55	PD8	bidirectional	GPIO PD8, 5 V tolerant. Alt: FSMC_D13; Remap: USART3_TX.
56	PD9	bidirectional	GPIO PD9, 5 V tolerant. Alt: FSMC_D14; Remap: USART3_RX.
57	PD10	bidirectional	GPIO PD10, 5 V tolerant. Alt: FSMC_D15; Remap: USART3_CK.
58	PD11	bidirectional	GPIO PD11, 5 V tolerant. Alt: FSMC_A16; Remap: USART3_CTS.
59	PD12	bidirectional	GPIO PD12, 5 V tolerant. Alt: FSMC_A17; Remap: TIM4_CH1 / USART3_RTS.
60	PD13	bidirectional	GPIO PD13, 5 V tolerant. Alt: FSMC_A18; Remap: TIM4_CH2.
61	PD14	bidirectional	GPIO PD14, 5 V tolerant. Alt: FSMC_D0; Remap: TIM4_CH3.
62	PD15	bidirectional	GPIO PD15, 5 V tolerant. Alt: FSMC_D1; Remap: TIM4_CH4.
63	PC6	bidirectional	GPIO PC6, 5 V tolerant. Alt: I2S2_MCK, TIM8_CH1, SDIO_D6; Remap: TIM3_CH1.
64	PC7	bidirectional	GPIO PC7, 5 V tolerant. Alt: I2S3_MCK, TIM8_CH2, SDIO_D7; Remap: TIM3_CH2.
65	PC8	bidirectional	GPIO PC8, 5 V tolerant. Alt: TIM8_CH3, SDIO_D0; Remap: TIM3_CH3.
66	PC9	bidirectional	GPIO PC9, 5 V tolerant. Alt: TIM8_CH4, SDIO_D1; Remap: TIM3_CH4.
67	PA8	bidirectional	GPIO PA8, 5 V tolerant. Alt: USART1_CK, TIM1_CH1, MCO (master clock output).
68	PA9	bidirectional	GPIO PA9, 5 V tolerant. Alt: USART1_TX, TIM1_CH2.
69	PA10	bidirectional	GPIO PA10, 5 V tolerant. Alt: USART1_RX, TIM1_CH3.
70	PA11	bidirectional	GPIO PA11, 5 V tolerant. Alt: USART1_CTS, USBDM (USB D-), CAN_RX, TIM1_CH4.
71	PA12	bidirectional	GPIO PA12, 5 V tolerant. Alt: USART1_RTS, USBDP (USB D+), CAN_TX, TIM1_ETR.
72	PA13	bidirectional	GPIO PA13, 5 V tolerant. Default alt after reset: JTMS-SWDIO (SW/JTAG data). Remap: PA13.
73	NC	unconnected	Not connected on LQFP100.
74	VSS_2	power_in	Digital ground (0 V).
75	VDD_2	power_in	Digital supply, 2.0-3.6 V.
76	PA14	bidirectional	GPIO PA14, 5 V tolerant. Default alt after reset: JTCK-SWCLK (SW/JTAG clock). Remap: PA14.
77	PA15	bidirectional	GPIO PA15, 5 V tolerant. Default alt after reset: JTDI. Alt: SPI3_NSS, I2S3_WS; Remap: TIM2_CH1_ETR, PA15, SPI1_NSS.
78	PC10	bidirectional	GPIO PC10, 5 V tolerant. Alt: UART4_TX, SDIO_D2; Remap: USART3_TX.
79	PC11	bidirectional	GPIO PC11, 5 V tolerant. Alt: UART4_RX, SDIO_D3; Remap: USART3_RX.
80	PC12	bidirectional	GPIO PC12, 5 V tolerant. Alt: UART5_TX, SDIO_CK; Remap: USART3_CK.
81	PD0	bidirectional	GPIO PD0, 5 V tolerant. Alt: FSMC_D2; Remap: CAN_RX. (On LQFP100 PD0 is available by default without OSC remap.)
82	PD1	bidirectional	GPIO PD1, 5 V tolerant. Alt: FSMC_D3; Remap: CAN_TX. (On LQFP100 PD1 is available by default without OSC remap.)
83	PD2	bidirectional	GPIO PD2, 5 V tolerant. Alt: TIM3_ETR, UART5_RX, SDIO_CMD.
84	PD3	bidirectional	GPIO PD3, 5 V tolerant. Alt: FSMC_CLK; Remap: USART2_CTS.
85	PD4	bidirectional	GPIO PD4, 5 V tolerant. Alt: FSMC_NOE; Remap: USART2_RTS.
86	PD5	bidirectional	GPIO PD5, 5 V tolerant. Alt: FSMC_NWE; Remap: USART2_TX.
87	PD6	bidirectional	GPIO PD6, 5 V tolerant. Alt: FSMC_NWAIT; Remap: USART2_RX.
88	PD7	bidirectional	GPIO PD7, 5 V tolerant. Alt: FSMC_NE1 / FSMC_NCE2; Remap: USART2_CK.
89	PB3	bidirectional	GPIO PB3, 5 V tolerant. Default alt after reset: JTDO. Alt: SPI3_SCK, I2S3_CK; Remap: PB3/TRACESWO, TIM2_CH2, SPI1_SCK.
90	PB4	bidirectional	GPIO PB4, 5 V tolerant. Default alt after reset: NJTRST. Alt: SPI3_MISO; Remap: PB4, TIM3_CH1, SPI1_MISO.
91	PB5	bidirectional	GPIO PB5 (not 5 V tolerant). Alt: I2C1_SMBA, SPI3_MOSI, I2S3_SD; Remap: TIM3_CH2, SPI1_MOSI.
92	PB6	bidirectional	GPIO PB6, 5 V tolerant. Alt: I2C1_SCL, TIM4_CH1; Remap: USART1_TX.
93	PB7	bidirectional	GPIO PB7, 5 V tolerant. Alt: I2C1_SDA, FSMC_NADV, TIM4_CH2; Remap: USART1_RX.
94	BOOT0	input	Boot mode select input sampled at reset (together with BOOT1/PB2). Selects Flash, System memory, or SRAM as boot source.
95	PB8	bidirectional	GPIO PB8, 5 V tolerant. Alt: TIM4_CH3, SDIO_D4; Remap: I2C1_SCL, CAN_RX.
96	PB9	bidirectional	GPIO PB9, 5 V tolerant. Alt: TIM4_CH4, SDIO_D5; Remap: I2C1_SDA, CAN_TX.
97	PE0	bidirectional	GPIO PE0, 5 V tolerant. Alt: TIM4_ETR, FSMC_NBL0.
98	PE1	bidirectional	GPIO PE1, 5 V tolerant. Alt: FSMC_NBL1.
99	VSS_3	power_in	Digital ground (0 V).
100	VDD_3	power_in	Digital supply, 2.0-3.6 V.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-100(14x14)
Category	MCU
Pins	100

Ordering variants

Same part, different packaging or reel option.

STM32F103VCT6
STM32F103VCT6VCT7
STM32F103VCT6VDT6
STM32F103VCT6VDT7
STM32F103VCT6VET6
STM32F103VCT6VET7
STM32F103VCT6VCH6
STM32F103VCT6VCH7
STM32F103VCT6VDH6
STM32F103VCT6VDH7
STM32F103VCT6VEH6
STM32F103VCT6VEH7
STM32F103VCT6RCT6
STM32F103VCT6RCT7
STM32F103VCT6RDT6
STM32F103VCT6RDT7
STM32F103VCT6RET6
STM32F103VCT6RET7
STM32F103VCT6RCY6TR
STM32F103VCT6RDY6TR
STM32F103VCT6REY6TR
STM32F103VCT6ZCT6
STM32F103VCT6ZCT7
STM32F103VCT6ZDT6
STM32F103VCT6ZDT7
STM32F103VCT6ZET6
STM32F103VCT6ZET7
STM32F103VCT6ZCH6
STM32F103VCT6ZCH7
STM32F103VCT6ZDH6
STM32F103VCT6ZDH7
STM32F103VCT6ZEH6
STM32F103VCT6ZEH7

CAD (KiCad official)

Symbol: STM32F103VCT6
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (143 pp, sha256 c61db5e362b62f2f, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF