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STM32F103CBT6TR

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by Ray

STMicroelectronics Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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STM32F103CBT6TR

STMicroelectronics · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · LQFP-48(7x7)

STM32F103CBT6TR from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Battery backup supply for RTC, external 32 kHz oscillator and backup registers when VDD is off. 1.8 V to 3.6 V.
2 PC13-TAMPER-RTC bidirectional General-purpose I/O PC13, also tamper detect input / RTC alarm/second output. Supplied from the switched backup domain; sink current limited to 3 mA and max 2 MHz on output, max load 30 pF.
3 PC14-OSC32_IN bidirectional General-purpose I/O PC14, also LSE 32.768 kHz oscillator input when the LSE is enabled. Backup-domain switched supply, output speed limited to 2 MHz / 30 pF.
4 PC15-OSC32_OUT bidirectional General-purpose I/O PC15, also LSE 32.768 kHz oscillator output when the LSE is enabled. Backup-domain switched supply, output speed limited to 2 MHz / 30 pF.
5 PD0-OSC_IN bidirectional HSE crystal oscillator input by default after reset in this package; can be remapped to GPIO PD0 (CANRX alt-function). Output-mode speed limited to 50 MHz.
6 PD1-OSC_OUT bidirectional HSE crystal oscillator output by default after reset in this package; can be remapped to GPIO PD1 (CANTX alt-function). Output-mode speed limited to 50 MHz.
7 NRST bidirectional Active-low bidirectional device reset with internal weak pull-up. Drive low >20 us to reset; released by internal power/reset circuitry after POR.
8 VSSA power_in Analog ground reference for ADCs and analog reference. Connect to system ground through a clean return path.
9 VDDA power_in Analog supply for ADCs, reset block, RCs and PLL. 2.0 V to 3.6 V, must be applied together with VDD and typically equal to VDD.
10 PA0-WKUP bidirectional GPIO PA0, WKUP input for Standby wake-up, and alt-functions USART2_CTS / ADC12_IN0 / TIM2_CH1_ETR. 5 V-tolerant is NOT set on this pin (analog-capable).
11 PA1 bidirectional GPIO PA1, alt-functions USART2_RTS / ADC12_IN1 / TIM2_CH2.
12 PA2 bidirectional GPIO PA2, alt-functions USART2_TX / ADC12_IN2 / TIM2_CH3.
13 PA3 bidirectional GPIO PA3, alt-functions USART2_RX / ADC12_IN3 / TIM2_CH4.
14 PA4 bidirectional GPIO PA4, alt-functions SPI1_NSS / USART2_CK / ADC12_IN4.
15 PA5 bidirectional GPIO PA5, alt-functions SPI1_SCK / ADC12_IN5.
16 PA6 bidirectional GPIO PA6, alt-functions SPI1_MISO / ADC12_IN6 / TIM3_CH1, remap TIM1_BKIN.
17 PA7 bidirectional GPIO PA7, alt-functions SPI1_MOSI / ADC12_IN7 / TIM3_CH2, remap TIM1_CH1N.
18 PB0 bidirectional GPIO PB0, alt-functions ADC12_IN8 / TIM3_CH3, remap TIM1_CH2N.
19 PB1 bidirectional GPIO PB1, alt-functions ADC12_IN9 / TIM3_CH4, remap TIM1_CH3N.
20 PB2/BOOT1 bidirectional GPIO PB2, also BOOT1 boot-mode selection sampled at reset together with BOOT0.
21 PB10 bidirectional GPIO PB10, alt-functions I2C2_SCL / USART3_TX, remap TIM2_CH3. 5 V-tolerant.
22 PB11 bidirectional GPIO PB11, alt-functions I2C2_SDA / USART3_RX, remap TIM2_CH4. 5 V-tolerant.
23 VSS_1 power_in Digital ground (VSS domain 1).
24 VDD_1 power_in Digital I/O and internal regulator supply (VDD domain 1). 2.0 V to 3.6 V.
25 PB12 bidirectional GPIO PB12, alt-functions SPI2_NSS / I2C2_SMBAI / USART3_CK / TIM1_BKIN. 5 V-tolerant.
26 PB13 bidirectional GPIO PB13, alt-functions SPI2_SCK / USART3_CTS / TIM1_CH1N. 5 V-tolerant.
27 PB14 bidirectional GPIO PB14, alt-functions SPI2_MISO / USART3_RTS / TIM1_CH2N. 5 V-tolerant.
28 PB15 bidirectional GPIO PB15, alt-functions SPI2_MOSI / TIM1_CH3N. 5 V-tolerant.
29 PA8 bidirectional GPIO PA8, alt-functions USART1_CK / TIM1_CH1 / MCO (master clock output). 5 V-tolerant.
30 PA9 bidirectional GPIO PA9, alt-functions USART1_TX / TIM1_CH2. 5 V-tolerant.
31 PA10 bidirectional GPIO PA10, alt-functions USART1_RX / TIM1_CH3. 5 V-tolerant.
32 PA11 bidirectional GPIO PA11, alt-functions USART1_CTS / CANRX / USBDM / TIM1_CH4. Shared USB D- and CAN RX; select one peripheral at a time. 5 V-tolerant.
33 PA12 bidirectional GPIO PA12, alt-functions USART1_RTS / CANTX / USBDP / TIM1_ETR. Shared USB D+ and CAN TX; select one peripheral at a time. 5 V-tolerant.
34 PA13 bidirectional After reset: JTMS/SWDIO serial-wire and JTAG data. Can be released to GPIO PA13 by disabling JTAG-SW debug. 5 V-tolerant.
35 VSS_2 power_in Digital ground (VSS domain 2).
36 VDD_2 power_in Digital I/O and internal regulator supply (VDD domain 2). 2.0 V to 3.6 V.
37 PA14 bidirectional After reset: JTCK/SWCLK serial-wire and JTAG clock. Can be released to GPIO PA14 by disabling JTAG-SW debug. 5 V-tolerant.
38 PA15 bidirectional After reset: JTDI. Alt-functions include TIM2_CH1_ETR / PA15 / SPI1_NSS remap. 5 V-tolerant.
39 PB3 bidirectional After reset: JTDO / TRACESWO. Alt-functions include TIM2_CH2 / SPI1_SCK remap. 5 V-tolerant.
40 PB4 bidirectional After reset: NJTRST (active-low JTAG reset with pull-up). Alt-functions TIM3_CH1 / SPI1_MISO remap. 5 V-tolerant.
41 PB5 bidirectional GPIO PB5, alt-functions I2C1_SMBAI, remap TIM3_CH2 / SPI1_MOSI. NOT 5 V-tolerant (only standard-tolerant on this pin).
42 PB6 bidirectional GPIO PB6, alt-functions I2C1_SCL / TIM4_CH1, remap USART1_TX. 5 V-tolerant.
43 PB7 bidirectional GPIO PB7, alt-functions I2C1_SDA / TIM4_CH2, remap USART1_RX. 5 V-tolerant.
44 BOOT0 input Boot-mode selection input sampled at reset with BOOT1(PB2): selects boot from Flash / System memory / SRAM.
45 PB8 bidirectional GPIO PB8, alt-function TIM4_CH3, remap I2C1_SCL / CANRX. 5 V-tolerant.
46 PB9 bidirectional GPIO PB9, alt-function TIM4_CH4, remap I2C1_SDA / CANTX. 5 V-tolerant.
47 VSS_3 power_in Digital ground (VSS domain 3).
48 VDD_3 power_in Digital I/O and internal regulator supply (VDD domain 3). 2.0 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-48(7x7)
Category PMIC
Pins 48

Ordering variants

Same part, different packaging or reel option.

  • STM32F103CBT6TR
  • STM32F103CBT6TRC8T6
  • STM32F103CBT6TRC8T6TR
  • STM32F103CBT6TRCBU6
  • STM32F103CBT6TRCBU6TR
  • STM32F103CBT6TRC8U6
  • STM32F103CBT6TRC8U6TR
  • STM32F103CBT6TRT8U6
  • STM32F103CBT6TRTBU6
  • STM32F103CBT6TRRBT6
  • STM32F103CBT6TRR8T6
  • STM32F103CBT6TRRBH6
  • STM32F103CBT6TRR8H6
  • STM32F103CBT6TRVBT6
  • STM32F103CBT6TRV8T6
  • STM32F103CBT6TRZBH6
  • STM32F103CBT6TRZ8H6
  • STM32F103CBT6TRZBY6
  • STM32F103CBT6TRZ8Y6

CAD (KiCad official)

  • Symbol: STM32F103CBT6TR
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (116 pp, sha256 0596dd57693c93d2, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF