STM32F103CBT6
Public Unreviewedby Ray
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdownSTM32F103CBT6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
STM32F103CBT6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup battery supply, 1.8 V to 3.6 V. Powers the RTC, LSE oscillator and backup registers when VDD is off. |
| 2 | PC13-TAMPER-RTC | bidirectional | GPIO PC13 with alternate function TAMPER input / RTC calibration output. Supplied through the backup power switch (limited to 3 mA, ≤2 MHz, ≤30 pF). |
| 3 | PC14-OSC32_IN | bidirectional | GPIO PC14; alternate function LSE 32.768 kHz oscillator input (OSC32_IN). Backup-domain supply, limited drive when used as GPIO. |
| 4 | PC15-OSC32_OUT | bidirectional | GPIO PC15; alternate function LSE 32.768 kHz oscillator output (OSC32_OUT). Backup-domain supply, limited drive when used as GPIO. |
| 5 | PD0-OSC_IN | bidirectional | Configured as OSC_IN (HSE crystal input) after reset. Can be remapped as GPIO PD0 (limited to 50 MHz in output). |
| 6 | PD1-OSC_OUT | bidirectional | Configured as OSC_OUT (HSE crystal output) after reset. Can be remapped as GPIO PD1 (limited to 50 MHz in output). |
| 7 | NRST | bidirectional | Bidirectional device reset (active low). Internal pull-up; asserted by internal reset sources. |
| 8 | VSSA | power_in | Analog ground reference for the ADC and analog blocks. Tie to system ground with proper decoupling. |
| 9 | VDDA | power_in | Analog supply for the ADC, reset block, PLL and oscillators, 2.0-3.6 V. Must be present whenever VDD is powered. |
| 10 | PA0-WKUP | bidirectional | GPIO PA0 with WKUP wake-from-standby input; alt: USART2_CTS, ADC12_IN0, TIM2_CH1_ETR. |
| 11 | PA1 | bidirectional | GPIO PA1; alt: USART2_RTS, ADC12_IN1, TIM2_CH2. |
| 12 | PA2 | bidirectional | GPIO PA2; alt: USART2_TX, ADC12_IN2, TIM2_CH3. |
| 13 | PA3 | bidirectional | GPIO PA3; alt: USART2_RX, ADC12_IN3, TIM2_CH4. |
| 14 | PA4 | bidirectional | GPIO PA4; alt: SPI1_NSS, USART2_CK, ADC12_IN4. |
| 15 | PA5 | bidirectional | GPIO PA5; alt: SPI1_SCK, ADC12_IN5. |
| 16 | PA6 | bidirectional | GPIO PA6; alt: SPI1_MISO, ADC12_IN6, TIM3_CH1, TIM1_BKIN (remap). |
| 17 | PA7 | bidirectional | GPIO PA7; alt: SPI1_MOSI, ADC12_IN7, TIM3_CH2, TIM1_CH1N (remap). |
| 18 | PB0 | bidirectional | GPIO PB0; alt: ADC12_IN8, TIM3_CH3, TIM1_CH2N (remap). |
| 19 | PB1 | bidirectional | GPIO PB1; alt: ADC12_IN9, TIM3_CH4, TIM1_CH3N (remap). |
| 20 | PB2 | bidirectional | GPIO PB2 (5 V tolerant), doubles as BOOT1 boot-mode select at reset. |
| 21 | PB10 | bidirectional | GPIO PB10 (5 V tolerant); alt: I2C2_SCL, USART3_TX, TIM2_CH3 (remap). |
| 22 | PB11 | bidirectional | GPIO PB11 (5 V tolerant); alt: I2C2_SDA, USART3_RX, TIM2_CH4 (remap). |
| 23 | VSS_1 | power_in | Digital ground return. Tie to system ground. |
| 24 | VDD_1 | power_in | Digital supply 2.0-3.6 V. Decouple locally with a 100 nF capacitor. |
| 25 | PB12 | bidirectional | GPIO PB12 (5 V tolerant); alt: SPI2_NSS, I2C2_SMBAl, USART3_CK, TIM1_BKIN (remap). |
| 26 | PB13 | bidirectional | GPIO PB13 (5 V tolerant); alt: SPI2_SCK, USART3_CTS, TIM1_CH1N (remap). |
| 27 | PB14 | bidirectional | GPIO PB14 (5 V tolerant); alt: SPI2_MISO, USART3_RTS, TIM1_CH2N (remap). |
| 28 | PB15 | bidirectional | GPIO PB15 (5 V tolerant); alt: SPI2_MOSI, TIM1_CH3N (remap). |
| 29 | PA8 | bidirectional | GPIO PA8 (5 V tolerant); alt: USART1_CK, TIM1_CH1, MCO (main clock output). |
| 30 | PA9 | bidirectional | GPIO PA9 (5 V tolerant); alt: USART1_TX, TIM1_CH2. |
| 31 | PA10 | bidirectional | GPIO PA10 (5 V tolerant); alt: USART1_RX, TIM1_CH3. |
| 32 | PA11 | bidirectional | GPIO PA11 (5 V tolerant); alt: USART1_CTS, CANRX, USBDM (USB D-), TIM1_CH4. |
| 33 | PA12 | bidirectional | GPIO PA12 (5 V tolerant); alt: USART1_RTS, CANTX, USBDP (USB D+), TIM1_ETR. |
| 34 | PA13 | bidirectional | SWDIO / JTMS after reset (SWD data / JTAG mode select). Usable as GPIO PA13 (5 V tolerant) once debug alternate is disabled. |
| 35 | VSS_2 | power_in | Digital ground return. Tie to system ground. |
| 36 | VDD_2 | power_in | Digital supply 2.0-3.6 V. Decouple locally with a 100 nF capacitor. |
| 37 | PA14 | bidirectional | SWCLK / JTCK after reset (SWD/JTAG clock). Usable as GPIO PA14 (5 V tolerant) once debug alternate is disabled. |
| 38 | PA15 | bidirectional | JTDI after reset. Alt: TIM2_CH1_ETR, SPI1_NSS (remap); usable as GPIO PA15 (5 V tolerant) once JTAG disabled. |
| 39 | PB3 | bidirectional | JTDO / TRACESWO after reset. Alt: TIM2_CH2 (remap), SPI1_SCK (remap); usable as GPIO PB3 (5 V tolerant) once JTAG disabled. |
| 40 | PB4 | bidirectional | NJTRST after reset. Alt: TIM3_CH1 (remap), SPI1_MISO (remap); usable as GPIO PB4 (5 V tolerant) once JTAG disabled. |
| 41 | PB5 | bidirectional | GPIO PB5 (not 5 V tolerant); alt: I2C1_SMBAl, TIM3_CH2 (remap), SPI1_MOSI (remap). |
| 42 | PB6 | bidirectional | GPIO PB6 (5 V tolerant); alt: I2C1_SCL, TIM4_CH1, USART1_TX (remap). |
| 43 | PB7 | bidirectional | GPIO PB7 (5 V tolerant); alt: I2C1_SDA, TIM4_CH2, USART1_RX (remap). |
| 44 | BOOT0 | input | Boot-mode select input sampled at reset with BOOT1 (PB2). Selects boot from Flash, system memory or SRAM. |
| 45 | PB8 | bidirectional | GPIO PB8 (5 V tolerant); alt: I2C1_SCL (remap), TIM4_CH3, CANRX (remap). |
| 46 | PB9 | bidirectional | GPIO PB9 (5 V tolerant); alt: I2C1_SDA (remap), TIM4_CH4, CANTX (remap). |
| 47 | VSS_3 | power_in | Digital ground return. Tie to system ground. |
| 48 | VDD_3 | power_in | Digital supply 2.0-3.6 V. Decouple locally with a 100 nF capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-48(7x7) |
| Category | MCU |
| Pins | 48 |
Ordering variants
Same part, different packaging or reel option.
STM32F103CBT6STM32F103CBT6CBT7STM32F103CBT6CBU6STM32F103CBT6TBU6STM32F103CBT6RBT6STM32F103CBT6RBH6STM32F103CBT6VBT6
CAD (KiCad official)
- Symbol:
STM32F103CBT6 - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
stm32f103cbt6.step |
617 KB | You want the bare part, or you mark your own boards. |
stm32f103cbt6-etched.step |
4.8 MB | You want the part with STM32F103CBT6 already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1195 faces against 747 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (105 pp, sha256
ceab0f159ae79118, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).