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STM32F100C6T6BTR

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by Ray

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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STM32F100C6T6BTR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM32F100C6T6BTR from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup battery supply for RTC, LSE oscillator and backup registers when VDD is off. Typical 1.8-3.6 V.
2 PC13-TAMPER-RTC bidirectional GPIO PC13 in backup domain; alternate: TAMPER input and RTC alarm output. Supplied through the backup power switch; limited drive (max 2 MHz, 30 pF, no LED load).
3 PC14-OSC32_IN bidirectional LSE (32.768 kHz) crystal input; alternate GPIO PC14. Backup-domain pin with restricted GPIO drive.
4 PC15-OSC32_OUT bidirectional LSE (32.768 kHz) crystal output; alternate GPIO PC15. Backup-domain pin with restricted GPIO drive.
5 PD0-OSC_IN bidirectional HSE (4-24 MHz) crystal input after reset; remappable to GPIO PD0 via software.
6 PD1-OSC_OUT bidirectional HSE (4-24 MHz) crystal output after reset; remappable to GPIO PD1 via software.
7 NRST bidirectional Active-low device reset. Bidirectional (internal pull-up ~40 kΩ); asserting low forces MCU into reset.
8 VSSA power_in Analog ground for ADC, DAC and reset/PVD block.
9 VDDA power_in Analog supply for ADC, DAC, reset block, PLL and RC oscillators. 2.0-3.6 V, tied to VDD.
10 PA0-WKUP bidirectional GPIO PA0; alternate: WKUP (wake-from-Standby), USART2_CTS, ADC1_IN0, TIM2_CH1_ETR.
11 PA1 bidirectional GPIO PA1; alternate: USART2_RTS, ADC1_IN1, TIM2_CH2.
12 PA2 bidirectional GPIO PA2; alternate: USART2_TX, ADC1_IN2, TIM2_CH3, TIM15_CH1.
13 PA3 bidirectional GPIO PA3; alternate: USART2_RX, ADC1_IN3, TIM2_CH4, TIM15_CH2.
14 PA4 bidirectional GPIO PA4; alternate: SPI1_NSS, USART2_CK, ADC1_IN4, DAC1_OUT.
15 PA5 bidirectional GPIO PA5; alternate: SPI1_SCK, ADC1_IN5, DAC2_OUT.
16 PA6 bidirectional GPIO PA6; alternate: SPI1_MISO, ADC1_IN6, TIM3_CH1, TIM1_BKIN, TIM16_CH1.
17 PA7 bidirectional GPIO PA7; alternate: SPI1_MOSI, ADC1_IN7, TIM3_CH2, TIM1_CH1N, TIM17_CH1.
18 PB0 bidirectional GPIO PB0; alternate: ADC1_IN8, TIM3_CH3, TIM1_CH2N.
19 PB1 bidirectional GPIO PB1; alternate: ADC1_IN9, TIM3_CH4, TIM1_CH3N.
20 PB2/BOOT1 bidirectional GPIO PB2 (5 V-tolerant); doubles as BOOT1 sampling input at reset to select boot memory.
21 PB10 bidirectional GPIO PB10 (5 V-tolerant); alternate: USART3_TX, TIM2_CH3, HDMI_CEC. I2C2_SCL not available on low-density value line.
22 PB11 bidirectional GPIO PB11 (5 V-tolerant); alternate: USART3_RX, TIM2_CH4. I2C2_SDA not available on low-density value line.
23 VSS_1 power_in Digital ground (pair with VDD_1).
24 VDD_1 power_in Digital supply, 2.0-3.6 V (pair with VSS_1). Requires 100 nF decoupling.
25 PB12 bidirectional GPIO PB12 (5 V-tolerant); alternate: TIM1_BKIN, USART3_CK. SPI2/I2C2 alternates not available on low-density value line.
26 PB13 bidirectional GPIO PB13 (5 V-tolerant); alternate: TIM1_CH1N, USART3_CTS. SPI2_SCK not available on low-density value line.
27 PB14 bidirectional GPIO PB14 (5 V-tolerant); alternate: TIM1_CH2N, USART3_RTS, TIM15_CH1. SPI2_MISO not available on low-density value line.
28 PB15 bidirectional GPIO PB15 (5 V-tolerant); alternate: TIM1_CH3N, TIM15_CH1N, TIM15_CH2. SPI2_MOSI not available on low-density value line.
29 PA8 bidirectional GPIO PA8 (5 V-tolerant); alternate: USART1_CK, MCO (master clock output), TIM1_CH1.
30 PA9 bidirectional GPIO PA9 (5 V-tolerant); alternate: USART1_TX, TIM1_CH2, TIM15_BKIN.
31 PA10 bidirectional GPIO PA10 (5 V-tolerant); alternate: USART1_RX, TIM1_CH3, TIM17_BKIN.
32 PA11 bidirectional GPIO PA11 (5 V-tolerant); alternate: USART1_CTS, TIM1_CH4.
33 PA12 bidirectional GPIO PA12 (5 V-tolerant); alternate: USART1_RTS, TIM1_ETR.
34 PA13/JTMS-SWDIO bidirectional SWD data / JTAG TMS after reset (5 V-tolerant); remappable to GPIO PA13.
35 VSS_2 power_in Digital ground (pair with VDD_2).
36 VDD_2 power_in Digital supply, 2.0-3.6 V (pair with VSS_2). Requires 100 nF decoupling.
37 PA14/JTCK-SWCLK bidirectional SWD clock / JTAG TCK after reset (5 V-tolerant); remappable to GPIO PA14.
38 PA15/JTDI bidirectional JTAG data-in after reset (5 V-tolerant); remap options: GPIO PA15, TIM2_CH1_ETR, SPI1_NSS.
39 PB3/JTDO bidirectional JTAG data-out / TRACESWO after reset (5 V-tolerant); remap options: GPIO PB3, TIM2_CH2, SPI1_SCK.
40 PB4/NJTRST bidirectional JTAG reset (active-low) after reset (5 V-tolerant); remap options: GPIO PB4, TIM3_CH1, SPI1_MISO.
41 PB5 bidirectional GPIO PB5 (not 5 V-tolerant); alternate: I2C1_SMBA, TIM16_BKIN, TIM3_CH2, SPI1_MOSI.
42 PB6 bidirectional GPIO PB6 (5 V-tolerant); alternate: I2C1_SCL, TIM16_CH1N, USART1_TX. TIM4 alternates not available on low-density value line.
43 PB7 bidirectional GPIO PB7 (5 V-tolerant); alternate: I2C1_SDA, TIM17_CH1N, USART1_RX. TIM4 alternates not available on low-density value line.
44 BOOT0 input Boot-mode select input sampled at reset (with PB2/BOOT1) to choose main Flash, system memory, or embedded SRAM boot.
45 PB8 bidirectional GPIO PB8 (5 V-tolerant); alternate: TIM16_CH1, CEC, I2C1_SCL (remap). TIM4_CH3 not available on low-density value line.
46 PB9 bidirectional GPIO PB9 (5 V-tolerant); alternate: TIM17_CH1, I2C1_SDA (remap). TIM4_CH4 not available on low-density value line.
47 VSS_3 power_in Digital ground (pair with VDD_3).
48 VDD_3 power_in Digital supply, 2.0-3.6 V (pair with VSS_3). Requires 100 nF decoupling.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-48(7x7)
Category MCU
Pins 48

Ordering variants

Same part, different packaging or reel option.

  • STM32F100C6T6BTR
  • STM32F100C6T6BTRC6T7B
  • STM32F100C6T6BTRC6T7BTR
  • STM32F100C6T6BTRR6T6B
  • STM32F100C6T6BTRR6T6BTR
  • STM32F100C6T6BTRR6T7B
  • STM32F100C6T6BTRR6T7BTR
  • STM32F100C6T6BTRV8T6B
  • STM32F100C6T6BTRV8T7B
  • STM32F100C6T6BTRVBT6B
  • STM32F100C6T6BTRVBT7B
  • STM32F100C6T6BTRRxHxB

CAD (KiCad official)

  • Symbol: STM32F100C6T6BTR
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (96 pp, sha256 360e3be010cabad4, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF