component
SSP9451
Public Made by Adomby adom
Shanghai Siproin Microelectronics DC-DC Converters, SOT-23-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSSP9451
Shanghai Siproin Microelectronics · DC-DC Converters · SOT-23-6
SSP9451 from Shanghai Siproin Microelectronics, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BST | passive | Bootstrap. Positive supply for the internal floating high-side MOSFET driver. Connect a bypass capacitor between this pin and SW; the internal bootstrap regulator holds this rail ~5V above SW (BST-to-SW absolute max 6.0V). |
| 2 | GND | power_in | Ground return. Should be connected as close as possible to the output capacitor to avoid high-current switching paths. |
| 3 | FB | input | Feedback input to the error amplifier. An external resistive divider from VOUT to GND is compared to the internal 0.794V (typ) reference to set the regulation voltage. |
| 4 | EN | input | Enable input. Pull above the enable threshold (Venh 1.6V min, 2.0V max) to enable; pull below to disable. Internally pulled to ground when floating; internally clamped to ~7.5V. Connect a 100kΩ resistor to VIN to auto-enable. |
| 5 | VIN | power_in | Input supply, 4.2V to 40V operating (absolute max 43V). Powers all internal control circuits and the high-side switching MOSFET. Requires a decoupling capacitor to GND placed close to this pin to reduce switching spikes. |
| 6 | SW | output | Switch node - output of the internal high-side MOSFET drain. Connect the inductor here and a low-VF Schottky catch diode to GND close to this pin. Absolute max VSW = VIN(MAX)+0.3V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Shanghai Siproin Microelectronics |
| Package | SOT-23-6 |
| Category | PMIC |
| Pins | 6 |
Ordering variants
Same part, different packaging or reel option.
SSP9451
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback Voltage | Vfb | 0.778 | 0.794 | 0.81 | V | 5 | |
| Oscillator Frequency | Fosc | 1.4 | 1.8 | 2.2 | MHz | 5 | |
| Minimum Operating Voltage | Vin min | 4.2 | V | 5 | |||
| UVLO Up Threshold | Vin(UVLO) | 3.3 | 4.2 | V | 5 | ||
| Enable up threshold | Venh | 1.6 | 2 | V | 5 | ||
| Upper Switch Leakage | Iswleak | 0.1 | 1 | μA | Ven=0V, Vsw=0V | 5 | |
| Shutdown Current | Isd | 3 | 15 | μA | Ven<0.3V | 5 | |
| Upper Switch ON Resistance | Rsw | 500 | mΩ | Vbst-Vsw=5V | 5 | ||
| Limiting Current | Ilim | 1 | A | 5 | |||
| Transconductance | Gcs | 3 | A/V | COMP to SENSE | 5 | ||
| Quiescent Current | Isq | 200 | μA | Vfb=0.9V,No load | 5 | ||
| UVLO Hysteresis | Vin(UVLO)hys | 0.8 | V | 5 | |||
| Soft-Start Time | Tss | 0.5 | ms | FB from 0 to1.8V | 5 | ||
| Minimum Switch ON Time | Ton min | 100 | ns | 5 | |||
| Thermal Shutdown Temp | 150 | ℃ | 5 | ||||
| Enable Threshold Hysteresis | En hys | 0.6 | V | 5 | |||
| Enable Clamp Voltage | En Vclamp | 7.5 | V | 5 | |||
| Supply Voltage | VIN | -0.3 | 43 | V | 4 | ||
| Switch Voltage | VSW | -0.3 | V | 4 | |||
| BST to SW | -0.3 | 6 | V | 4 | |||
| All Other Pins | -0.3 | 5 | V | 4 | |||
| Continuous Power Dissipation | PD | 0.57 | W | TA=+25℃ | 4 | ||
| Junction Temperature | T | 150 | ℃ | 4 | |||
| Lead Temperature | T | 260 | ℃ | 4 | |||
| Storage Temperature | TSTG | -65 | 150 | ℃ | 4 | ||
| Operating Junction Temperature | TJ | -40 | 125 | ℃ | 4 | ||
| Junction-to-Ambient Thermal Resistance | θJA | 220 | ℃/W | 4 | |||
| Junction-to-Case Thermal Resistance | θJC | 110 | ℃/W | 4 | |||
| Supply Voltage (recommended) | VIN | 4.2 | 40 | V | 4 | ||
| Switch Voltage (recommended) | VSW | 40 | V | 4 |
CAD (KiCad official)
- Symbol:
SSP9451 - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
ssp9451-etched.step/ssp9451-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ssp9451.step/ssp9451.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
ssp9451.step |
97 KB | You want the bare part, or you mark your own boards. |
ssp9451-etched.step |
1.7 MB | You want the part with SSP9451 already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 409 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Shanghai Siproin Microelectronics datasheet (13 pp, sha256
7829d7b5652b6515, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).