SSP485N from Shanghai Siproin Microelectronics, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RO	output	Receiver output. When RE is low, RO is driven high if A-B >= +0.1V, low if A-B <= -0.1V, and high (fail-safe) if A/B are open or shorted. Output logic sense inverts automatically if A and B are physically swapped on the bus (polarity adaptation).
2	RE	input	Receiver output enable, active low. RO is enabled when RE is low; RO is high-impedance when RE is high. Typically tied low for continuous receive, or driven by the same MCU pin as DE for half-duplex direction control.
3	DE	input	Driver output enable, active high. Bus outputs A and B are enabled when DE is high; both go high-impedance when DE is low. Commonly tied to /RE for MCU-driven half-duplex TX/RX steering.
4	DI	input	Driver input (TTL/CMOS). With DE high and A wired to bus A: DI low drives A low and B high; DI high drives A high and B low. Logic sense inverts automatically when A/B are physically swapped on the bus (polarity adaptation).
5	GND	power_in	Ground reference for logic and bus signaling. Connect to the local 0V rail; in isolated networks it becomes the 485GND reference for pull-up/pull-down bias network.
6	A	bidirectional	Non-inverting RS-485 bus line: receiver input and driver output. Absolute voltage rating -13 V to +15 V; differential threshold ±100 mV; receiver input resistance >=96 kOhm (1/8 unit load). Polarity assignment relative to B is auto-detected 78 ms after power-on.
7	B	bidirectional	Inverting RS-485 bus line: receiver input and driver output. Absolute voltage rating -13 V to +15 V; complementary to A. Polarity relative to A is determined automatically by the on-chip polarity-adaptation circuit.
8	VDD	power_in	Positive supply, +5V typical (4.5V to 5.5V operating range, 7V absolute max). Quiescent supply current ~520 uA (DE high) / ~430 uA (DE low). Decouple locally with a 0.1 uF ceramic capacitor to GND.

Key specifications

Parameter	Value
Manufacturer	Shanghai Siproin Microelectronics
Package	SOP-8
Category	Interface
Pins	8

Ordering variants

Same part, different packaging or reel option.

SSP485N

CAD (KiCad official)

Symbol: SSP485N
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`ssp485n.step`	122 KB	You want the bare part, or you mark your own boards.
`ssp485n-etched.step`	1.9 MB	You want the part with `SSP485N` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 456 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Shanghai Siproin Microelectronics datasheet (10 pp, sha256 ed3c328b4c0cfd81, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF