SP706TEN-L from MaxLinear, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MR	input	Manual Reset (active LOW). Triggers a 200ms reset pulse when pulled below 0.8V. Has internal ~70µA pull-up to VCC; can be driven by TTL/CMOS logic or a switch to ground.
2	VCC	power_in	Voltage Input. Operating range 1.0V to 5.5V (SP70xT typical 3.0-5.5V). Supply current typically 25µA at 3.3V.
3	GND	power_in	Ground reference for all signals.
4	PFI	input	Power-Fail comparator Input. When voltage on this pin is less than the 1.25V internal reference, PFO goes LOW. Connect PFI to GND or VCC when unused.
5	PFO	output	Power-Fail comparator Output (active LOW). Output is LOW until PFI is greater than 1.25V. Typical drive: ISOURCE=500µA at VCC<3.6V, ISINK=1.2mA.
6	WDI	input	Watchdog Input. If this input stays HIGH or LOW for 1.6s, the watchdog times out and WDO goes LOW. Floating WDI or tri-stating it disables the watchdog. Timer clears on any rising/falling edge or while RESET is asserted.
7	RESET	output	Active-LOW RESET output. Pulses LOW for 200ms when triggered and stays LOW whenever VCC is below the 3.08V reset threshold. Remains LOW for 200ms after VCC rises above threshold or MR goes HIGH. Watchdog timeout only triggers RESET if WDO is tied to MR.
8	WDO	output	Watchdog Output (active LOW). Pulls LOW when the internal 1.6s watchdog timer expires and remains LOW until the watchdog is cleared. Also goes LOW during low-line conditions and while VCC is below the reset threshold; no minimum pulse width. Returns HIGH with no delay once VCC recovers.

Key specifications

Parameter	Value
Manufacturer	MaxLinear
Package	SOIC-8
Category	PMIC
Pins	8

Ordering variants

Same part, different packaging or reel option.

SP706TEN-L
SP706TEN-L/TR
SP706TEN-LTCN-L
SP706TEN-LTCN-L/TR
SP706TEN-LTEU-L
SP706TEN-LTEU-L/TR
SP706TEN-LTCU-L
SP706TEN-LTCU-L/TR

CAD (KiCad official)

Symbol: SP706TEN-L
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`sp706ten-l.step`	122 KB	You want the bare part, or you mark your own boards.
`sp706ten-l-etched.step`	1.8 MB	You want the part with `SP706TEN-L` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 447 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: MaxLinear datasheet (17 pp, sha256 2bdbc0752cea3816, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF