SP3222EEY-L from MaxLinear, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	EN	input	Receiver Enable (active-low). Apply logic LOW for normal operation; drive HIGH to force the receiver outputs (R1OUT, R2OUT) into a high-impedance (high-Z) state. TTL/CMOS logic level referenced to VCC.
2	C1+	passive	Positive terminal of the voltage-doubler charge-pump flying capacitor. Connect a 0.1µF ceramic capacitor between C1+ and C1-.
3	V+	power_out	+5.5V output generated by the internal charge pump (voltage doubler). Bypass to GND (or VCC) with a 0.1µF capacitor. Used internally to power the RS-232 driver positive rail.
4	C1-	passive	Negative terminal of the voltage-doubler charge-pump flying capacitor. Connect a 0.1µF ceramic capacitor between C1+ and C1-.
5	C2+	passive	Positive terminal of the inverting charge-pump flying capacitor. Connect a 0.1µF ceramic capacitor between C2+ and C2-.
6	C2-	passive	Negative terminal of the inverting charge-pump flying capacitor. Connect a 0.1µF ceramic capacitor between C2+ and C2-.
7	V-	power_out	-5.5V output generated by the internal charge pump (inverter). Bypass to GND (or VCC) with a 0.1µF capacitor. Used internally to power the RS-232 driver negative rail.
8	T2OUT	output	RS-232 driver #2 output. Drives an RS-232-compatible line with a typical output swing of ±5.4V into a 3kΩ load. Short-circuit protected (continuous to GND).
9	R2IN	input	RS-232 receiver #2 input. Accepts ±15V (up to ±25V absolute max) RS-232 line levels; internal 5kΩ (typ) input resistance to GND. Interoperable down to a 2.7V RS-232 source.
10	R2OUT	output	TTL/CMOS receiver #2 output. Rail-to-rail CMOS output referenced to VCC; goes high-Z when EN is HIGH (SP3222E only). VOH ≥ VCC−0.6V at −1mA, VOL ≤ 0.4V at 1.6mA.
11	N.C.	unconnected	No internal connection. Leave floating or tie to any convenient net; not electrically connected to the die.
12	T2IN	input	TTL/CMOS driver #2 input. Logic level referenced to VCC; VIL ≤ 0.8V, VIH ≥ 2.0V (VCC=3.3V) or ≥ 2.4V (VCC=5.0V). Typical input hysteresis 250mV.
13	T1IN	input	TTL/CMOS driver #1 input. Logic level referenced to VCC; VIL ≤ 0.8V, VIH ≥ 2.0V (VCC=3.3V) or ≥ 2.4V (VCC=5.0V). Typical input hysteresis 250mV.
14	N.C.	unconnected	No internal connection. Leave floating or tie to any convenient net; not electrically connected to the die.
15	R1OUT	output	TTL/CMOS receiver #1 output. Rail-to-rail CMOS output referenced to VCC; goes high-Z when EN is HIGH (SP3222E only). VOH ≥ VCC−0.6V at −1mA, VOL ≤ 0.4V at 1.6mA.
16	R1IN	input	RS-232 receiver #1 input. Accepts ±15V (up to ±25V absolute max) RS-232 line levels; internal 5kΩ (typ) input resistance to GND. Interoperable down to a 2.7V RS-232 source.
17	T1OUT	output	RS-232 driver #1 output. Drives an RS-232-compatible line with a typical output swing of ±5.4V into a 3kΩ load. Short-circuit protected (continuous to GND).
18	GND	power_in	Device ground reference (0V). All logic and RS-232 signals are referenced to this pin.
19	VCC	power_in	Primary supply input, 3.0V to 5.5V. Bypass to GND with a 0.1µF ceramic capacitor placed close to the pin. Absolute max −0.3V to +6.0V.
20	SHDN	input	Shutdown control input (active-low). Drive HIGH for normal operation; drive LOW to shut down the drivers (T1OUT/T2OUT high-Z) and disable the on-board charge-pump power supply, dropping supply current to <1µA (SP3222E only).

Key specifications

Parameter	Value
Manufacturer	MaxLinear
Package	TSSOP-20
Category	Interface
Pins	20

Ordering variants

Same part, different packaging or reel option.

SP3222EEY-LECY-L/TR
SP3222EEY-L/TR
SP3222EEY-LECA-L/TR
SP3222EEY-LEEA-L/TR
SP3222EEY-LECT-L/TR

CAD (KiCad official)

Symbol: SP3222EEY-L
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`sp3222eey-l.step`	267 KB	You want the bare part, or you mark your own boards.
`sp3222eey-l-etched.step`	2.7 MB	You want the part with `SP3222EEY-L` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 679 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: MaxLinear datasheet (21 pp, sha256 657cf6a156b351de, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF