SN75LBC184DR from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	R	output	Receiver output. Drives logic HIGH when V(A) - V(B) >= 0.2 V (asserted differential), LOW when V(A) - V(B) <= -0.2 V, high-impedance when /RE is HIGH, and HIGH (fail-safe) when the A/B inputs are open. IOH = -8 mA, IOL = 4 mA.
2	/RE	input	Receiver output enable, active LOW. LOW enables the receiver output R; HIGH places R in high-impedance. Recommended VIH >= 2 V, VIL <= 0.8 V.
3	DE	input	Driver enable, active HIGH. HIGH enables the differential bus driver so A/B follow D; LOW disables the driver and places A/B in high-impedance. Recommended VIH >= 2 V, VIL <= 0.8 V.
4	D	input	Driver data input. When DE is HIGH: D=HIGH drives A HIGH / B LOW, D=LOW drives A LOW / B HIGH. Slew-rate-controlled output stage limits data rate to ~250 kbps to allow longer stubs in noisy environments.
5	GND	power_in	Ground reference for supply and logic. Also the return for the on-chip transient voltage suppression network on A/B (protected to +/-15 kV air-gap ESD and 400-W surge).
6	A	bidirectional	Non-inverting differential bus I/O (RS-485/RS-422). Driver output when DE is HIGH, receiver non-inverting input when /RE is LOW. Continuous voltage tolerance -15 V to +15 V; recommended common-mode range -7 V to +12 V. Includes integrated TVS clamping.
7	B	bidirectional	Inverting differential bus I/O (RS-485/RS-422). Driver output when DE is HIGH, receiver inverting input when /RE is LOW. Continuous voltage tolerance -15 V to +15 V; recommended common-mode range -7 V to +12 V. Includes integrated TVS clamping.
8	VCC	power_in	Positive supply voltage. Recommended 4.75 V to 5.25 V (5 V nominal). ICC typ 12 mA active, 175 uA (300 uA max) with the driver and receiver both disabled.

Key specifications

Parameter	Value
Manufacturer	UMW
Package	SOP-8
Category	Interface
Pins	8

Ordering variants

Same part, different packaging or reel option.

SN75LBC184DRD
SN75LBC184DR
SN75LBC184DRP

CAD (KiCad official)

Symbol: SN75LBC184DR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`sn75lbc184dr.step`	122 KB	You want the bare part, or you mark your own boards.
`sn75lbc184dr-etched.step`	2.4 MB	You want the part with `SN75LBC184DR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 594 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: UMW datasheet (23 pp, sha256 53d77bcd7a987620, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF