SN74LVTH245APWR
Public Unreviewedby Ray
Texas Instruments Buffer/Driver/Transceiver, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.
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README
markdownSN74LVTH245APWR
Texas Instruments · Buffer/Driver/Transceiver · TSSOP-20
SN74LVTH245APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIR | input | Direction control. When DIR=L, data flows from B to A; when DIR=H, data flows from A to B. TTL-compatible input, VIH ≥ 2 V, VIL ≤ 0.8 V. |
| 2 | A1 | bidirectional | Channel-1 A-side bus port. Input or 3-state output depending on DIR and /OE. Includes active bus-hold circuitry to hold unused inputs at a valid logic level. |
| 3 | A2 | bidirectional | Channel-2 A-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 4 | A3 | bidirectional | Channel-3 A-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 5 | A4 | bidirectional | Channel-4 A-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 6 | A5 | bidirectional | Channel-5 A-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 7 | A6 | bidirectional | Channel-6 A-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 8 | A7 | bidirectional | Channel-7 A-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 9 | A8 | bidirectional | Channel-8 A-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 10 | GND | power_in | Device ground reference (0 V). |
| 11 | B8 | bidirectional | Channel-8 B-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 12 | B7 | bidirectional | Channel-7 B-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 13 | B6 | bidirectional | Channel-6 B-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 14 | B5 | bidirectional | Channel-5 B-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 15 | B4 | bidirectional | Channel-4 B-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 16 | B3 | bidirectional | Channel-3 B-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 17 | B2 | bidirectional | Channel-2 B-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 18 | B1 | bidirectional | Channel-1 B-side bus port. Input or 3-state output depending on DIR and /OE. Includes bus-hold. |
| 19 | /OE | input | Active-low output enable. When /OE=L the transceiver is enabled and drives the destination bus per DIR; when /OE=H both A and B ports are in the high-impedance (isolation) state. Should be tied to VCC through a pull-up during power sequencing to guarantee Hi-Z at power-up/down. |
| 20 | VCC | power_in | 3.3-V supply input. Recommended VCC = 2.7 V to 3.6 V; absolute max 4.6 V. Bypass locally with a 0.1 µF ceramic to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Ordering variants
Same part, different packaging or reel option.
SN74LVTH245APWRSN74LVTH245APWRAPWE4SN74LVTH245APWRAPWG4SN74LVTH245APWRE4SN74LVTH245APWRG4SN74LVTH245APWRADBRSN74LVTH245APWRADBR.BSN74LVTH245APWRADBR1G4SN74LVTH245APWRADBR1G4.BSN74LVTH245APWRADWSN74LVTH245APWRADWRSN74LVTH245APWRADW.BSN74LVTH245APWRADWR.BSN74LVTH245APWRADWRG4SN74LVTH245APWRANSRSN74LVTH245APWRANS.BSN74LVTH245APWRANSR.BSN74LVTH245APWRANSRG4SN74LVTH245APWRARGYRSN74LVTH245APWRARGYR.BSN74LVTH245APWRARGYRG4SN74LVTH245APWRARGYRG4.BSN74LVTH245APWRAFKSN74LVTH245APWRAJSN74LVTH245APWRAWSN74LVTH245APWRAGQNRSN74LVTH245APWRAZQNR
CAD (KiCad official)
- Symbol:
SN74LVTH245APWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
sn74lvth245apwr.step |
267 KB | You want the bare part, or you mark your own boards. |
sn74lvth245apwr-etched.step |
2.9 MB | You want the part with SN74LVTH245APWR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 761 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
7af52ff8d823ffed, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).