SN74LVC573APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Output-enable pin, active-low. When high, the eight Q outputs are placed in the high-impedance state; when low, the outputs are enabled to drive their stored/latched data.
2	1D	input	D-type latch data input 1. Transparent to 1Q when LE is high; latched on the high-to-low transition of LE.
3	2D	input	D-type latch data input 2. Transparent to 2Q when LE is high; latched on the high-to-low transition of LE.
4	3D	input	D-type latch data input 3. Transparent to 3Q when LE is high; latched on the high-to-low transition of LE.
5	4D	input	D-type latch data input 4. Transparent to 4Q when LE is high; latched on the high-to-low transition of LE.
6	5D	input	D-type latch data input 5. Transparent to 5Q when LE is high; latched on the high-to-low transition of LE.
7	6D	input	D-type latch data input 6. Transparent to 6Q when LE is high; latched on the high-to-low transition of LE.
8	7D	input	D-type latch data input 7. Transparent to 7Q when LE is high; latched on the high-to-low transition of LE.
9	8D	input	D-type latch data input 8. Transparent to 8Q when LE is high; latched on the high-to-low transition of LE.
10	GND	power_in	Device ground reference (0 V). Continuous current through VCC or GND is limited to ±100 mA.
11	LE	input	Latch enable input. When high, the eight latches are transparent (Q follows D); on the high-to-low transition, data present at the D inputs is stored in the latches.
12	8Q	tri_state	3-state latched data output 8. Drives 8D data when OE is low; high-impedance when OE is high. IOL/IOH up to ±24 mA at VCC = 3 V.
13	7Q	tri_state	3-state latched data output 7. Drives 7D data when OE is low; high-impedance when OE is high.
14	6Q	tri_state	3-state latched data output 6. Drives 6D data when OE is low; high-impedance when OE is high.
15	5Q	tri_state	3-state latched data output 5. Drives 5D data when OE is low; high-impedance when OE is high.
16	4Q	tri_state	3-state latched data output 4. Drives 4D data when OE is low; high-impedance when OE is high.
17	3Q	tri_state	3-state latched data output 3. Drives 3D data when OE is low; high-impedance when OE is high.
18	2Q	tri_state	3-state latched data output 2. Drives 2D data when OE is low; high-impedance when OE is high.
19	1Q	tri_state	3-state latched data output 1. Drives 1D data when OE is low; high-impedance when OE is high.
20	VCC	power_in	Supply voltage. Operating range 1.65 V to 3.6 V for SN74LVC573A; inputs accept up to 5.5 V for level-translation applications. Decouple locally with a 0.1 µF ceramic.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Logic
Pins	20

Ordering variants

Same part, different packaging or reel option.

SN74LVC573APWR
SN74LVC573APWRDW
SN74LVC573APWRDWR
SN74LVC573APWRDB
SN74LVC573APWRDBR
SN74LVC573APWRDGV
SN74LVC573APWRDGVR
SN74LVC573APWRN
SN74LVC573APWRNS
SN74LVC573APWRNSR
SN74LVC573APWRRGY
SN74LVC573APWRRGYR
SN74LVC573APWRFK
SN74LVC573APWRGQN
SN74LVC573APWRZQN

CAD (KiCad official)

Symbol: SN74LVC573APWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (38 pp, sha256 1d245c329ee342b0, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF