SN74LVC244APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1OE	input	Active-low output enable for the first 4-bit buffer (1Y1-1Y4). When low, outputs are enabled; when high, outputs are in high-impedance (Hi-Z) state.
2	1A1	input	Port 1A1 input to the first 4-bit buffer channel 1. Accepts input voltages up to 5.5V regardless of VCC.
3	2Y4	tri_state	Port 2Y4 buffered output from the second 4-bit buffer channel 4. 3-state; enabled by 2OE low. Drives up to ±24mA at VCC=3V.
4	1A2	input	Port 1A2 input to the first 4-bit buffer channel 2. Accepts input voltages up to 5.5V.
5	2Y3	tri_state	Port 2Y3 buffered output from the second 4-bit buffer channel 3. 3-state; enabled by 2OE low.
6	1A3	input	Port 1A3 input to the first 4-bit buffer channel 3. Accepts input voltages up to 5.5V.
7	2Y2	tri_state	Port 2Y2 buffered output from the second 4-bit buffer channel 2. 3-state; enabled by 2OE low.
8	1A4	input	Port 1A4 input to the first 4-bit buffer channel 4. Accepts input voltages up to 5.5V.
9	2Y1	tri_state	Port 2Y1 buffered output from the second 4-bit buffer channel 1. 3-state; enabled by 2OE low.
10	GND	power_in	Ground return for the device. Connect to the system 0V reference.
11	2A1	input	Port 2A1 input to the second 4-bit buffer channel 1. Accepts input voltages up to 5.5V.
12	1Y4	tri_state	Port 1Y4 buffered output from the first 4-bit buffer channel 4. 3-state; enabled by 1OE low.
13	2A2	input	Port 2A2 input to the second 4-bit buffer channel 2. Accepts input voltages up to 5.5V.
14	1Y3	tri_state	Port 1Y3 buffered output from the first 4-bit buffer channel 3. 3-state; enabled by 1OE low.
15	2A3	input	Port 2A3 input to the second 4-bit buffer channel 3. Accepts input voltages up to 5.5V.
16	1Y2	tri_state	Port 1Y2 buffered output from the first 4-bit buffer channel 2. 3-state; enabled by 1OE low.
17	2A4	input	Port 2A4 input to the second 4-bit buffer channel 4. Accepts input voltages up to 5.5V.
18	1Y1	tri_state	Port 1Y1 buffered output from the first 4-bit buffer channel 1. 3-state; enabled by 1OE low.
19	2OE	input	Active-low output enable for the second 4-bit buffer (2Y1-2Y4). When low, outputs are enabled; when high, outputs are in high-impedance (Hi-Z) state.
20	VCC	power_in	Supply voltage input. Operating range 1.65V to 3.6V (data retention down to 1.5V). Bypass with a 100nF ceramic capacitor close to the pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Logic
Pins	20

Ordering variants

Same part, different packaging or reel option.

SN74LVC244APWR
SN74LVC244APWRDB
SN74LVC244APWRDBR
SN74LVC244APWRDGV
SN74LVC244APWRDGVR
SN74LVC244APWRDW
SN74LVC244APWRDWR
SN74LVC244APWRN
SN74LVC244APWRNS
SN74LVC244APWRNSR
SN74LVC244APWRDGS
SN74LVC244APWRDGSR
SN74LVC244APWRRGY
SN74LVC244APWRRGYR
SN74LVC244APWRRKS
SN74LVC244APWRRKSR
SN74LVC244APWRRWP
SN74LVC244APWRRWPR
SN74LVC244APWRZQN
SN74LVC244APWRZQNR

CAD (KiCad official)

Symbol: SN74LVC244APWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`sn74lvc244apwr.step`	267 KB	You want the bare part, or you mark your own boards.
`sn74lvc244apwr-etched.step`	2.8 MB	You want the part with `SN74LVC244APWR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 739 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (50 pp, sha256 5196fbace1069cc2, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF