SN74LVC1G86DBVR from UMW, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	INA	input	XOR gate logic input A. Over-voltage tolerant: VIN may be between 0 and 7.0V regardless of VCC (0.5-5.5V). TTL/LVCMOS compatible.
2	INB	input	XOR gate logic input B. Over-voltage tolerant: VIN may be between 0 and 7.0V regardless of VCC (0.5-5.5V). TTL/LVCMOS compatible.
3	GND	power_in	Ground reference (0 V).
4	OUTY	output	XOR gate output Y = A ⊕ B. Push-pull CMOS output with 24 mA sink capability (VOL ≤ 0.55V at IOL=24mA, VCC=3V). Pull-up may be tied between 0 and 7.0V.
5	VCC	power_in	Positive supply, 1.65 V to 5.5 V (operating). Recommend a 0.1 µF decoupling capacitor to GND placed close to the pin.

Key specifications

Parameter	Value
Manufacturer	UMW
Package	SOT-23-5
Category	Logic
Pins	5

Ordering variants

Same part, different packaging or reel option.

SN74LVC1G86DBVR
SN74LVC1G86DBVRDCKR

CAD (KiCad official)

Symbol: SN74LVC1G86DBVR
Footprint: Package_TO_SOT_SMD:SOT-23-5
3D model: SOT-23-5 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`sn74lvc1g86dbvr.step`	85 KB	You want the bare part, or you mark your own boards.
`sn74lvc1g86dbvr-etched.step`	2.4 MB	You want the part with `SN74LVC1G86DBVR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 601 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: UMW datasheet (12 pp, sha256 c8149b8b2f74d58d, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF