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Contents

README

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SN74LVC1G373DCKR

Texas Instruments · Latches · SC-70-6(SOT-363)

SN74LVC1G373DCKR from Texas Instruments, in a SC-70-6(SOT-363). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LE input Latch Enable input. When LE is high, the Q output follows the D input (transparent mode). When LE is taken low, the current D value is latched and Q holds its state.
2 GND power_in Ground reference (0 V) for the device.
3 D input D latch data input. Sampled continuously while LE is high; latched on the falling edge of LE. CMOS-level input, tolerant to 5.5 V regardless of VCC.
4 Q tri_state Q latch output. Balanced high-drive CMOS push-pull output rated ±24 mA at 3.3 V. Placed in high-impedance state when /OE is high.
5 VCC power_in Positive supply rail. Recommended operating range 1.65 V to 5.5 V; absolute maximum 6.5 V. Bypass locally with a ceramic capacitor to GND.
6 /OE input Active-low output enable. Drive low to enable the Q output; drive high to place Q in the high-impedance (Hi-Z) state. Does not affect the internal latch contents.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SC-70-6(SOT-363)
Category Logic
Pins 6

Ordering variants

Same part, different packaging or reel option.

  • SN74LVC1G373DCKR
  • SN74LVC1G373DCKRDBV
  • SN74LVC1G373DCKRDBVR
  • SN74LVC1G373DCKRYZP
  • SN74LVC1G373DCKRYZPR

CAD (KiCad official)

  • Symbol: SN74LVC1G373DCKR
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SC-70-6(SOT-363) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 d33c16c3d219a30c, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF