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sn74lv32adr

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by Ray

Texas Instruments Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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README

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SN74LV32ADR

Texas Instruments · Gates · SOIC-14

SN74LV32ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A. CMOS logic input; VIH = VCC x 0.7, VIL = VCC x 0.3 (at VCC = 3 V to 5.5 V). Overvoltage tolerant up to 5.5 V at any valid VCC.
2 1B input Gate 1 input B. CMOS logic input; VIH = VCC x 0.7, VIL = VCC x 0.3 (at VCC = 3 V to 5.5 V). Overvoltage tolerant up to 5.5 V at any valid VCC.
3 1Y output Gate 1 output; Y = 1A OR 1B. Push-pull CMOS output; IOH = -12 mA / IOL = 12 mA at VCC = 4.5 V. Continuous per-output current should not exceed +/-25 mA.
4 2A input Gate 2 input A. CMOS logic input; VIH = VCC x 0.7, VIL = VCC x 0.3 (at VCC = 3 V to 5.5 V). Overvoltage tolerant up to 5.5 V at any valid VCC.
5 2B input Gate 2 input B. CMOS logic input; VIH = VCC x 0.7, VIL = VCC x 0.3 (at VCC = 3 V to 5.5 V). Overvoltage tolerant up to 5.5 V at any valid VCC.
6 2Y output Gate 2 output; Y = 2A OR 2B. Push-pull CMOS output; IOH = -12 mA / IOL = 12 mA at VCC = 4.5 V. Continuous per-output current should not exceed +/-25 mA.
7 GND power_in Device ground reference (0 V).
8 3Y output Gate 3 output; Y = 3A OR 3B. Push-pull CMOS output; IOH = -12 mA / IOL = 12 mA at VCC = 4.5 V. Continuous per-output current should not exceed +/-25 mA.
9 3A input Gate 3 input A. CMOS logic input; VIH = VCC x 0.7, VIL = VCC x 0.3 (at VCC = 3 V to 5.5 V). Overvoltage tolerant up to 5.5 V at any valid VCC.
10 3B input Gate 3 input B. CMOS logic input; VIH = VCC x 0.7, VIL = VCC x 0.3 (at VCC = 3 V to 5.5 V). Overvoltage tolerant up to 5.5 V at any valid VCC.
11 4Y output Gate 4 output; Y = 4A OR 4B. Push-pull CMOS output; IOH = -12 mA / IOL = 12 mA at VCC = 4.5 V. Continuous per-output current should not exceed +/-25 mA.
12 4A input Gate 4 input A. CMOS logic input; VIH = VCC x 0.7, VIL = VCC x 0.3 (at VCC = 3 V to 5.5 V). Overvoltage tolerant up to 5.5 V at any valid VCC.
13 4B input Gate 4 input B. CMOS logic input; VIH = VCC x 0.7, VIL = VCC x 0.3 (at VCC = 3 V to 5.5 V). Overvoltage tolerant up to 5.5 V at any valid VCC.
14 VCC power_in Supply voltage input, 2 V to 5.5 V (absolute max 7 V). Bypass with a 0.1 uF ceramic capacitor placed close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Ordering variants

  • SN74LV32ADRD
  • SN74LV32ADR
  • SN74LV32ADRDBR
  • SN74LV32ADRPW
  • SN74LV32ADRPWR
  • SN74LV32ADRPWRG4
  • SN74LV32ADRDGVR
  • SN74LV32ADRNSR
  • SN74LV32ADRRGYR

CAD (KiCad official)

  • Symbol: SN74LV32ADR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 44f13476edaf574b, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

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PCB Footprint

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Datasheet

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