SN74LS165ADR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SH/LD	input	Shift/Load control. Low = parallel-load data at A-H into the register (asynchronous, overrides clock). High = enable serial shifting on CLK/CLK INH. Diode-clamped TTL input, R_eq ~13 kΩ nom.
2	CLK	input	Clock input. On the rising edge (with CLK INH low and SH/LD high), data shifts from QA toward QH. CLK and CLK INH are combined in a two-input positive-NOR gate, so either may serve as clock or inhibit.
3	E	input	Parallel data input for bit E of the 8-bit word. Loaded into the corresponding stage when SH/LD is low. TTL input, R_eq ~24 kΩ nom.
4	F	input	Parallel data input for bit F of the 8-bit word. Loaded into the corresponding stage when SH/LD is low.
5	G	input	Parallel data input for bit G of the 8-bit word. Loaded into the corresponding stage when SH/LD is low.
6	H	input	Parallel data input for bit H (last stage) of the 8-bit word. Loaded into the QH stage when SH/LD is low; also drives the QH/QH-bar outputs directly after load.
7	QH_N	output	Complementary serial output (inverted QH). Provides the inverse of the eighth-stage register bit. Totem-pole TTL output, IOH = -800 μA, IOL = 16 mA, V_OL ≤ 0.4 V.
8	GND	power_in	Ground / 0 V reference for the device.
9	QH	output	Serial data output from the eighth register stage. During serial shift this bit is presented at QH; use as the serial-out for cascading multiple '165A devices. Totem-pole TTL output.
10	SER	input	Serial data input. Data at SER is shifted into the QA stage on each rising clock edge when SH/LD is high and CLK INH is low. Used to cascade '165A devices (connect prior stage's QH to next stage's SER).
11	A	input	Parallel data input for bit A (first stage) of the 8-bit word. Loaded into QA when SH/LD is low.
12	B	input	Parallel data input for bit B of the 8-bit word. Loaded when SH/LD is low.
13	C	input	Parallel data input for bit C of the 8-bit word. Loaded when SH/LD is low.
14	D	input	Parallel data input for bit D of the 8-bit word. Loaded when SH/LD is low.
15	CLK INH	input	Clock inhibit. When high, blocks the CLK input (positive-NOR gating). Should be transitioned high only while CLK is high to avoid producing spurious clock edges.
16	VCC	power_in	Positive supply, 4.75 V to 5.25 V (SN74LS165A). Typical ICC ≈ 42 mA (max 63 mA); typical power dissipation 90 mW.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

SN74LS165ADR
SN74LS165AN
SN74LS165ANSR
SN74LS165ADRSN54LS165AJ
SN74LS165ADRSNJ54LS165AJ
SN74LS165ADRSNJ54LS165AW
SN74LS165ADRSNJ54LS165AFK

CAD (KiCad official)

Symbol: SN74LS165ADR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`sn74ls165adr.step`	217 KB	You want the bare part, or you mark your own boards.
`sn74ls165adr-etched.step`	2.7 MB	You want the part with `SN74LS165ADR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 674 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (25 pp, sha256 1985012cf301bde1, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF